Analog Devices
ADuCM362
2024.06.03
Cortex-M3 Microcontroller Device
CM3
r2p1
little
3
false
8
32
ADI_ADC0
Analog to Digital Converter
ADC0
0x0
0x0
0x4C
registers
n
ADC0
13
ADC0ACC
32-bit accumulator register
0x3C
32
read-only
n
0x0
0x0
VALUE
TBD
0
32
ADC0ATH
Holds the threshold value for the accumulator comparator
0x40
32
read-write
n
0x0
0x0
VALUE
TBD
0
32
ADC0CON
Main control register
0x8
32
read-write
n
0x0
0x0
ADCCN
AIN- bits
0
5
AIN0
AIN0
0
AIN1
AIN1
1
AIN10
AIN10
10
AIN11
AIN11
11
DAC
DAC
12
AGND
AGND
15
TEMP
TEMP
17
AIN2
AIN2
2
AIN3
AIN3
3
AIN4
AIN4
4
AIN5
AIN5
5
AIN6
AIN6
6
AIN7
AIN7
7
AIN8
AIN8
8
AIN9
AIN9
9
ADCCODE
ADC Output Coding bits
18
1
INT
INT
0
UINT
UINT
1
ADCCP
AIN+ bits
5
5
AIN0
AIN0
0
AIN1
AIN1
1
AIN10
AIN10
10
AIN11
AIN11
11
DAC
DAC
12
AVDD4
AVDD4
13
IOVDD4
IOVDD4
14
AGND
AGND
15
TEMP
TEMP
16
AIN2
AIN2
2
AIN3
AIN3
3
AIN4
AIN4
4
AIN5
AIN5
5
AIN6
AIN6
6
AIN7
AIN7
7
AIN8
AIN8
8
AIN9
AIN9
9
ADCDIAG
Diagnostic Current bits bits
10
2
DIAG_OFF
DIAG_OFF
0
DIAG_POS
DIAG_POS
1
DIAG_NEG
DIAG_NEG
2
DIAG_ALL
DIAG_ALL
3
ADCEN
Enable Bit
19
1
DIS
DIS
0
EN
EN
1
ADCREF
Reference selection
12
2
INTREF
INTREF
0
EXTREF
EXTREF
1
EXTREF2
EXTREF2
2
AVDDREF
AVDDREF
3
BUFBYPN
Negative buffer bypass
14
1
DIS
DIS
0
EN
EN
1
BUFBYPP
Positive buffer bypass
15
1
DIS
DIS
0
EN
EN
1
BUFPOWN
Negative buffer power down
17
1
DIS
Disable powerdown - Negative buffer is enabled
0
EN
Enable powerdown - Negative buffer is disabled
1
BUFPOWP
Positive buffer power down
16
1
DIS
Disable powerdown - Positive buffer is enabled
0
EN
Enable powerdown - Positive buffer is disabled
1
ADC0DAT
conversion result register
0x48
32
read-only
n
0x0
0x0
VALUE
TBD
0
32
ADC0EXTGN
Gain calibration register when using external reference
0x14
16
read-write
n
0x0
0x0
VALUE
Gain with Ext Ref
0
16
ADC0FLT
Filter configuration register
0x20
16
read-write
n
0x0
0x0
AF
Averaging filter
8
4
CHOP
Enables System-Chopping bits
15
1
OFF
OFF
0
ON
ON
1
NOTCH2
Inserts a notch at FNOTCH2
7
1
DIS
DIS
0
EN
EN
1
RAVG2
Enables a running Average-By-2 bits
14
1
OFF
OFF
0
ON
ON
1
SF
SINC Filter value
0
7
SINC4EN
Enable the Sinc4 filter instead of Sinc3 filter.
12
1
DIS
DIS
0
EN
EN
1
ADC0INTGN
Gain calibration register when using internal reference
0x10
16
read-write
n
0x0
0x0
VALUE
Gain with Int Ref
0
16
ADC0MDE
mode control register
0x24
16
read-write
n
0x0
0x0
ADCMD
ADC Mode bits
0
3
OFF
OFF
0
CONT
CONT
1
SINGLE
SINGLE
2
IDLE
IDLE
3
INTOCAL
INTOCAL
4
INTGCAL
INTGCAL
5
SYSOCAL
SYSOCAL
6
SYSGCAL
SYSGCAL
7
ADCMOD2
ADC modulator gain of 2 control bits
3
1
MOD2OFF
MOD2OFF
0
MOD2ON
MOD2ON
1
PGA
PGA Gain Select bit
4
4
G1
G1
0
G2
G2
1
G4
G4
2
G8
G8
3
G16
G16
4
G32
G32
5
G64
G64
6
G128
G128
7
ADC0MSKI
Interrupt control register
0x4
8
read-write
n
0x0
0x0
ATHEX
ADC Accumulator Comparator Threshold status bit mask
3
1
DIS
DIS
0
EN
EN
1
OVR
ADC overrange bit mask.
1
1
DIS
DIS
0
EN
EN
1
RDY
valid conversion result mask
0
1
DIS
DIS
0
EN
EN
1
THEX
ADC comparator threshold mask
2
1
DIS
DIS
0
EN
EN
1
ADC0OF
Offset calibration register
0xC
16
read-write
n
0x0
0x0
VALUE
Offset
0
16
ADC0PRO
Configuration register for Post processing of ADC0 results
0x44
8
read-write
n
0x0
0x0
ACCEN
ADC Accumulator Enable bits
4
2
Off
Off
0
En
En
1
EnNDec
EnNDec
2
EnAccCnt
EnAccCnt
3
CMPEN
ADC Comparator Enable bits
2
2
Off
Off
0
En
En
1
EnCnt
EnCnt
2
EnCntDec
EnCntDec
3
OREN
ADC OverRange Enable
1
1
DIS
DIS
0
EN
EN
1
RCEN
ADC Result Counter Enable
0
1
DIS
DIS
0
EN
EN
1
ADC0RCR
Number of ADC0 conversions before an ADC interrupt is generated.
0x28
16
read-write
n
0x0
0x0
VALUE
TBD
0
16
ADC0RCV
This 16-bit, read-only MMR holds the current number of ADC0 conversion results
0x2C
16
read-only
n
0x0
0x0
VALUE
TBD
0
16
ADC0STA
ADC Status register
0x0
8
read-only
n
0x0
0x0
ATHEX
ADC Accumulator Comparator Threshold status bit.
3
1
DIS
DIS
0
EN
EN
1
CAL
ADC Calibration status register
5
1
DIS
DIS
0
EN
EN
1
ERR
ADC conversion error status bit.
4
1
DIS
DIS
0
EN
EN
1
OVR
ADC overrange bit.
1
1
DIS
DIS
0
EN
EN
1
RDY
valid conversion result
0
1
DIS
DIS
0
EN
EN
1
THEX
ADC comparator threshold.
2
1
DIS
DIS
0
EN
EN
1
ADC0TH
Sets the threshold
0x30
16
read-write
n
0x0
0x0
VALUE
TBD
0
16
ADC0THC
Determines how many cumulative ADC0 conversion result readings above ADC0TH must occur
0x34
8
read-write
n
0x0
0x0
VALUE
TBD
0
8
ADC0THV
8-bit threshold exceeded counter register
0x38
8
read-only
n
0x0
0x0
VALUE
TBD
0
8
ADC0VDDGN
Gain calibration register when using AVDD as the ADC reference
0x18
16
read-write
n
0x0
0x0
VALUE
Gain with Avdd Ref
0
16
ADCCFG
Control register for the VBIAS voltage generator, ground switch and external reference buffer
0x1C
16
read-write
n
0x0
0x0
BOOST30
Boost the Vbias current source ability by 30 times
13
1
DIS
DIS
0
EN
EN
1
EXTBUF
Control signals for ext_ref buffers bits
0
2
OFF
OFF
0
VREFPN
VREFPN
1
VREFP_VREF2P
VREFP_VREF2P
2
GNDSWON
GND_SW
7
1
DIS
DIS
0
EN
EN
1
GNDSWRESEN
20k resistor in series with GND_SW
6
1
DIS
DIS
0
EN
EN
1
PINSEL
Enable vbias generator, send vbias to selected ain pin bits
8
3
DIS
Disable VBIAS generator
0
AIN7
AIN7
4
AIN11
AIN11
6
SIMU
Enable both ADCs
15
1
DIS
DIS
0
EN
EN
1
ADI_ADC1
Analog to Digital Converter
ADC1
0x0
0x0
0x60
registers
n
ADC1
14
ADC1ACC
32-bit accumulator register
0x3C
32
read-only
n
0x0
0x0
VALUE
TBD
0
32
ADC1ATH
Holds the threshold value for the accumulator comparator
0x40
32
read-write
n
0x0
0x0
VALUE
TBD
0
32
ADC1CON
Main control register
0x8
32
read-write
n
0x0
0x0
ADCCN
AIN- bits
0
5
AIN0
AIN0
0
AIN1
AIN1
1
AIN10
AIN10
10
AIN11
AIN11
11
DAC
DAC
12
AGND
AGND
15
TEMP
TEMP
17
AIN2
AIN2
2
AIN3
AIN3
3
AIN4
AIN4
4
AIN5
AIN5
5
AIN6
AIN6
6
AIN7
AIN7
7
AIN8
AIN8
8
AIN9
AIN9
9
ADCCODE
ADC Output Coding bits
18
1
INT
INT
0
UINT
UINT
1
ADCCP
AIN+ bits
5
5
AIN0
AIN0
0
AIN1
AIN1
1
AIN10
AIN10
10
AIN11
AIN11
11
DAC
DAC
12
AVDD4
AVDD4
13
IOVDD4
IOVDD4
14
AGND
AGND
15
TEMP
TEMP
16
AIN2
AIN2
2
AIN3
AIN3
3
AIN4
AIN4
4
AIN5
AIN5
5
AIN6
AIN6
6
AIN7
AIN7
7
AIN8
AIN8
8
AIN9
AIN9
9
ADCDIAG
Diagnostic Current bits bits
10
2
DIAG_OFF
DIAG_OFF
0
DIAG_POS
DIAG_POS
1
DIAG_NEG
DIAG_NEG
2
DIAG_ALL
DIAG_ALL
3
ADCEN
Enable Bit
19
1
DIS
DIS
0
EN
EN
1
ADCREF
Reference selection
12
2
INTREF
INTREF
0
EXTREF
EXTREF
1
EXTREF2
EXTREF2
2
AVDDREF
AVDDREF
3
BUFBYPN
Negative buffer bypass
14
1
DIS
DIS
0
EN
EN
1
BUFBYPP
Positive buffer bypass
15
1
DIS
DIS
0
EN
EN
1
BUFPOWN
Negative buffer power down
17
1
DIS
Disable powerdown - Negative buffer is enabled
0
EN
Enable powerdown - Negative buffer is disabled
1
BUFPOWP
Positive buffer power down
16
1
DIS
Disable powerdown - Positive buffer is enabled
0
EN
Enable powerdown - Positive buffer is disabled
1
ADC1DAT
conversion result register
0x48
32
read-only
n
0x0
0x0
VALUE
TBD
0
32
ADC1EXTGN
Gain calibration register when using external reference
0x14
16
read-write
n
0x0
0x0
VALUE
Gain with Ext Ref
0
16
ADC1FLT
Filter configuration register
0x20
16
read-write
n
0x0
0x0
AF
Averaging filter
8
4
CHOP
Enables System-Chopping bits
15
1
OFF
OFF
0
ON
ON
1
NOTCH2
Inserts a notch at FNOTCH2
7
1
DIS
DIS
0
EN
EN
1
RAVG2
Enables a running Average-By-2 bits
14
1
OFF
OFF
0
ON
ON
1
SF
SINC Filter value
0
7
SINC4EN
Enable the Sinc4 filter instead of Sinc3 filter.
12
1
DIS
DIS
0
EN
EN
1
ADC1INTGN
Gain calibration register when using internal reference
0x10
16
read-write
n
0x0
0x0
VALUE
Gain with Int Ref
0
16
ADC1MDE
mode control register
0x24
16
read-write
n
0x0
0x0
ADCMD
ADC Mode bits
0
3
OFF
OFF
0
CONT
CONT
1
SINGLE
SINGLE
2
IDLE
IDLE
3
INTOCAL
INTOCAL
4
INTGCAL
INTGCAL
5
SYSOCAL
SYSOCAL
6
SYSGCAL
SYSGCAL
7
ADCMOD2
ADC modulator gain of 2 control bits
3
1
MOD2OFF
MOD2OFF
0
MOD2ON
MOD2ON
1
PGA
PGA Gain Select bit
4
4
G1
G1
0
G2
G2
1
G4
G4
2
G8
G8
3
G16
G16
4
G32
G32
5
G64
G64
6
G128
G128
7
ADC1MSKI
Interrupt control register
0x4
8
read-write
n
0x0
0x0
ATHEX
ADC Accumulator Comparator Threshold status bit mask
3
1
DIS
DIS
0
EN
EN
1
OVR
ADC overrange bit mask.
1
1
DIS
DIS
0
EN
EN
1
RDY
valid conversion result mask
0
1
DIS
DIS
0
EN
EN
1
THEX
ADC comparator threshold mask
2
1
DIS
DIS
0
EN
EN
1
ADC1OF
Offset calibration register
0xC
16
read-write
n
0x0
0x0
VALUE
Offset
0
16
ADC1PRO
Configuration register for Post processing of ADC1 results
0x44
8
read-write
n
0x0
0x0
ACCEN
ADC Accumulator Enable bits
4
2
Off
Off
0
En
En
1
EnNDec
EnNDec
2
EnAccCnt
EnAccCnt
3
CMPEN
ADC Comparator Enable bits
2
2
Off
Off
0
En
En
1
EnCnt
EnCnt
2
EnCntDec
EnCntDec
3
OREN
ADC OverRange Enable
1
1
DIS
DIS
0
EN
EN
1
RCEN
ADC Result Counter Enable
0
1
DIS
DIS
0
EN
EN
1
ADC1RCR
Number of ADC1 conversions before an ADC interrupt is generated.
0x28
16
read-write
n
0x0
0x0
VALUE
TBD
0
16
ADC1RCV
This 16-bit, read-only MMR holds the current number of ADC1 conversion results
0x2C
16
read-only
n
0x0
0x0
VALUE
TBD
0
16
ADC1STA
ADC Status register
0x0
8
read-only
n
0x0
0x0
ATHEX
ADC Accumulator Comparator Threshold status bit.
3
1
DIS
DIS
0
EN
EN
1
CAL
ADC Calibration status register
5
1
DIS
DIS
0
EN
EN
1
ERR
ADC conversion error status bit.
4
1
DIS
DIS
0
EN
EN
1
OVR
ADC overrange bit.
1
1
DIS
DIS
0
EN
EN
1
RDY
valid conversion result
0
1
DIS
DIS
0
EN
EN
1
THEX
ADC comparator threshold.
2
1
DIS
DIS
0
EN
EN
1
ADC1TH
Sets the threshold
0x30
16
read-write
n
0x0
0x0
VALUE
TBD
0
16
ADC1THC
Determines how many cumulative ADC1 conversion result readings above ADC1TH must occur
0x34
8
read-write
n
0x0
0x0
VALUE
TBD
0
8
ADC1THV
8-bit threshold exceeded counter register
0x38
8
read-only
n
0x0
0x0
VALUE
TBD
0
8
ADC1VDDGN
Gain calibration register when using AVDD as the ADC reference
0x18
16
read-write
n
0x0
0x0
VALUE
Gain with Avdd Ref
0
16
ADCSCFG1
Control register for the VBIAS voltage generator, ground switch and external reference buffer
0x1C
16
read-write
n
0x0
0x0
BOOST30
Boost the Vbias current source ability by 30 times
13
1
DIS
DIS
0
EN
EN
1
EXTBUF
Control signals for ext_ref buffers bits
0
2
OFF
OFF
0
VREFPN
VREFPN
1
VREFP_VREF2P
VREFP_VREF2P
2
GNDSWON
GND_SW
7
1
DIS
DIS
0
EN
EN
1
GNDSWRESEN
20k resistor in series with GND_SW
6
1
DIS
DIS
0
EN
EN
1
PINSEL
Enable vbias generator, send vbias to selected ain pin bits
8
3
DIS
Disable VBIAS generator
0
AIN7
AIN7
4
AIN11
AIN11
6
SIMU
Enable both ADCs
15
1
DIS
DIS
0
EN
EN
1
ADI_ADCDMA
Analog to Digital Converter
ADCDMA
0x0
0x0
0xC
registers
n
ADCDMACON
ADC DMA mode Configuration register
0x8
16
read-write
n
0x0
0x0
ADC0CTRL
TBD
0
1
DIS
DIS
0
EN
EN
1
ADC0DMAEN
TBD
1
1
DIS
DIS
0
EN
EN
1
ADC1CTRL
TBD
2
1
DIS
DIS
0
EN
EN
1
ADC1DMAEN
TBD
3
1
DIS
DIS
0
EN
EN
1
SINC2DMAEN
TBD
4
1
DIS
DIS
0
EN
EN
1
ADI_ADCSTEP
Analog to Digital Converter
ADCSTEP
0x0
0x0
0x10
registers
n
DETCON
Control register for reference detection and the step detection filter
0x0
16
read-write
n
0x0
0x0
ADCSEL
Select ADC
2
1
DIS
DIS
0
EN
EN
1
RATE
Control the sinc2 filter's time interval
0
2
REFDET
Enable external reference detection circuit
8
1
DIS
DIS
0
EN
EN
1
SINC2
Enable Sinc2 filter
7
1
DIS
DIS
0
EN
EN
1
STEPCTRL
Control the method to generate the step flag
3
1
DIS
DIS
0
EN
EN
1
DETSTA
Status register for detection
0x4
8
read-only
n
0x0
0x0
DATOF
STEPDAT Overflow
3
1
DIS
DIS
0
EN
EN
1
REFSTA
TBD
4
1
DIS
DIS
0
EN
EN
1
STEPDATRDY
TBD
0
1
DIS
DIS
0
EN
EN
1
STEPERR
TBD
2
1
DIS
DIS
0
EN
EN
1
STEPFLAG
TBD
1
1
DIS
DIS
0
EN
EN
1
STEPDAT
Offers coarse data from the output of the step detection filter
0xC
32
read-only
n
0x0
0x0
VALUE
TBD
0
32
STEPTH
Threshold for step detection filter
0x8
16
read-write
n
0x0
0x0
VALUE
TBD
0
9
ADI_ANA
Analog Control
ANA
0x0
0x0
0x78
registers
n
IEXCCON
Controls the on-chip Excitation Current Sources
0x40
8
read-write
n
0x0
0x0
IPSEL0
Select IEXC0 pin AIN- bits
0
3
Off
Off
0
AIN4
AIN4
4
AIN5
AIN5
5
AIN6
AIN6
6
AIN7
AIN7
7
IPSEL1
Select IEXC1 pin AIN- bits
3
3
Off
Off
0
AIN4
AIN4
4
AIN5
AIN5
5
AIN6
AIN6
6
AIN7
AIN7
7
PD
IEXC Power down- bits
7
1
off
off
0
En
En
1
REFSEL
IREF Source- bits
6
1
Ext
Ext
0
Int
Int
1
IEXCDAT
Sets the output current setting for both Excitation Current sources
0x44
8
read-write
n
0x0
0x0
IDAT
Output Current- bits
1
5
0uA
0uA
0
300uA
300uA
10
400uA
400uA
11
450uA
450uA
14
600uA
600uA
15
800uA
800uA
19
250uA
250uA
20
500uA
500uA
21
750uA
750uA
22
1mA
1mA
31
50uA
50uA
4
100uA
100uA
5
150uA
150uA
6
200uA
200uA
7
IDAT0
10uA Enable
0
1
DIS
DIS
0
EN
EN
1
REFCTRL
Internal Reference Control register
0x30
16
read-write
n
0x0
0x0
REFPD
Power down reference
0
1
DIS
DIS
0
EN
EN
1
ADI_CLKCTL
Clock Control
CLKCTL
0x0
0x0
0x448
registers
n
CLKCON0
System clocking architecture control register
0x0
16
read-write
n
0x0
0x0
CD
Clock divide bits
0
3
DIV1
DIV1
0
DIV2
DIV2
1
DIV4
DIV4
2
DIV8
DIV8
3
DIV16
DIV16
4
DIV32
DIV32
5
DIV64
DIV64
6
DIV128
DIV128
7
CLKMUX
Digital subsystem clock source select bits.
3
2
HFOSC
HFOSC
0
LFXTAL
LFXTAL
1
LFOSC
LFOSC
2
EXTCLK
EXTCLK
3
CLKOUT
GPIO output clock multiplexer select bits
5
3
UCLKCG
UCLKCG
0
UCLK
UCLK
1
PCLK
PCLK
2
HFOSC
HFOSC
5
LFOSC
LFOSC
6
LFXTAL
LFXTAL
7
CLKCON1
System Clocks Control Register 1
0x4
16
read-write
n
0x0
0x0
I2CCD
Clock divide bits for I2C system clock
6
3
DIV1
DIV1
0
DIV2
DIV2
1
DIV4
DIV4
2
DIV8
DIV8
3
DIV16
DIV16
4
DIV32
DIV32
5
DIV64
DIV64
6
DIV128
DIV128
7
PWMCD
Clock divide bits for PWM system clock
12
3
DIV1
DIV1
0
DIV2
DIV2
1
DIV4
DIV4
2
DIV8
DIV8
3
DIV16
DIV16
4
DIV32
DIV32
5
DIV64
DIV64
6
DIV128
DIV128
7
SPI0CD
Clock divide bits for SPI0 system clock
0
3
DIV1
DIV1
0
DIV2
DIV2
1
DIV4
DIV4
2
DIV8
DIV8
3
DIV16
DIV16
4
DIV32
DIV32
5
DIV64
DIV64
6
DIV128
DIV128
7
SPI1CD
Clock divide bits for SPI1 system clock
3
3
DIV1
DIV1
0
DIV2
DIV2
1
DIV4
DIV4
2
DIV8
DIV8
3
DIV16
DIV16
4
DIV32
DIV32
5
DIV64
DIV64
6
DIV128
DIV128
7
UART0CD
Clock divide bits for UART0 system clock
9
3
DIV1
DIV1
0
DIV2
DIV2
1
DIV4
DIV4
2
DIV8
DIV8
3
DIV16
DIV16
4
DIV32
DIV32
5
DIV64
DIV64
6
DIV128
DIV128
7
CLKCON2
System Clocks Control Register 2
0x3C
16
read-write
n
0x0
0x0
DACCD
Clock divide bits for DAC system clock
14
1
DIV8
None
0
DIV16
None
1
DISUART1CLK
Disable UART1 system clock
0
1
DIS
None
0
EN
None
1
DISUART2CLK
Disable UART2 system clock
1
1
DIS
None
0
EN
None
1
UART1CD
Clock divide bits for UART1 system clock
8
3
DIV1
None
0
DIV2
None
1
DIV4
None
2
DIV8
None
3
DIV16
None
4
DIV32
None
5
DIV64
None
6
DIV128
None
7
UART2CD
Clock divide bits for UART2 system clock
11
3
DIV1
None
0
DIV2
None
1
DIV4
None
2
DIV8
None
3
DIV16
None
4
DIV32
None
5
DIV64
None
6
DIV128
None
7
CLKDIS
System Clocks Control Register 1
0x2C
16
read-write
n
0x0
0x0
DISADCCLK
Disable ADC system clock
9
1
DIS
DIS
0
EN
EN
1
DISDACCLK
Disable DAC system clock
7
1
DIS
DIS
0
EN
EN
1
DISDMACLK
Disable DMA system clock
8
1
DIS
DIS
0
EN
EN
1
DISI2CCLK
Disable I2C system clock
2
1
DIS
DIS
0
EN
EN
1
DISPWMCLK
Disable PWM system clock
4
1
DIS
DIS
0
EN
EN
1
DISSPI0CLK
Disable SPI0 system clock bits
0
1
DIS
DIS
0
EN
EN
1
DISSPI1CLK
Disable SPI1 system clock
1
1
DIS
DIS
0
EN
EN
1
DIST0CLK
Disable Timer 0 system clock
5
1
DIS
DIS
0
EN
EN
1
DIST1CLK
Disable Timer 1 system clock
6
1
DIS
DIS
0
EN
EN
1
DISUART0CLK
Disable UART0 system clock
3
1
DIS
DIS
0
EN
EN
1
CLKSYSDIV
Sys Clock div Register
0x444
16
read-write
n
0x0
0x0
CLKSEL
Clock divide bits for root system clock
0
2
DIV1
None
0
DIV2
None
1
DIV4
None
2
DIV8
None
3
XOSCCON
Crystal Oscillator control
0x410
8
read-write
n
0x0
0x0
DIV2
Divide by two enable
2
1
DIS
DIS
0
EN
EN
1
ENABLE
Crystal oscillator circuit enable (Enable the oscillator circuitry.)
0
1
DIS
DIS
0
EN
EN
1
ADI_DAC
Digital To Analog Converter
DAC
0x0
0x0
0x5C
registers
n
DACCON
Control Register
0x0
16
read-write
n
0x0
0x0
BUFBYP
TBD
6
1
DIS
DIS
0
EN
EN
1
CLK
bits
5
1
HCLK
HCLK
0
Timer1
Timer1
1
CLR
bits
4
1
On
On
0
Off
Off
1
DMAEN
bits
10
1
Off
Off
0
On
On
1
MDE
Mode bits
2
2
12bit
12bit
0
16BitFast
16BitFast
2
16BitSlow
16BitSlow
3
NPN
TBD
8
1
DIS
DIS
0
EN
EN
1
PD
TBD
9
1
DIS
DIS
0
EN
EN
1
RNG
DAC Range bits
0
2
IntVref
IntVref
0
AVdd
AVdd
3
DACDAT
Data Register
0x4
32
read-write
n
0x0
0x0
VALUE
Data
12
20
ADI_DMA
Direct Memory Access
DMA
0x0
0x0
0x1000
registers
n
DMA_ERR
22
DMA_SPI1_TX
23
DMA_SPI1_RX
24
DMA_UART_TX
25
DMA_UART_RX
26
DMA_I2CS_TX
27
DMA_I2CS_RX
28
DMA_I2CM_TX
29
DMA_I2CM_RX
30
DMA_DAC
31
DMA_ADC0
32
DMA_ADC1
33
DMA_SINC2
34
DMAADBPTR
Channel alt control database pointer
0xC
32
read-only
n
0x0
0x0
ALTCBPTR
Pointer to the base address of the alternate data structure
0
32
DMAALTCLR
Channel Primary-Alternate Clear
0x34
32
write-only
n
0x0
0x0
ADC0
ADC0
9
1
DIS
DIS
0
EN
EN
1
ADC1
ADC1
10
1
DIS
DIS
0
EN
EN
1
DAC
DAC DMA Output
8
1
DIS
DIS
0
EN
EN
1
I2CMRX
DMA I2C Master RX
7
1
DIS
DIS
0
EN
EN
1
I2CMTX
DMA I2C Master TX
6
1
DIS
DIS
0
EN
EN
1
I2CSRX
DMA I2C Slave RX
5
1
DIS
DIS
0
EN
EN
1
I2CSTX
DMA I2C Slave TX
4
1
DIS
DIS
0
EN
EN
1
SINC2
SINC2 Output Step detection
11
1
DIS
DIS
0
EN
EN
1
SPI1RX
DMA SPI 1 RX
1
1
DIS
DIS
0
EN
EN
1
SPI1TX
DMA SPI 1 TX
0
1
DIS
DIS
0
EN
EN
1
UARTRX
DMA UART RX
3
1
DIS
DIS
0
EN
EN
1
UARTTX
DMA UART TX
2
1
DIS
DIS
0
EN
EN
1
DMAALTSET
Channel Primary-Alternate Set
0x30
32
read-write
n
0x0
0x0
ADC0
ADC0
9
1
DIS
DIS
0
EN
EN
1
ADC1
ADC1
10
1
DIS
DIS
0
EN
EN
1
DAC
DAC DMA Output
8
1
DIS
DIS
0
EN
EN
1
I2CMRX
DMA I2C Master RX
7
1
DIS
DIS
0
EN
EN
1
I2CMTX
DMA I2C Master TX
6
1
DIS
DIS
0
EN
EN
1
I2CSRX
DMA I2C Slave RX
5
1
DIS
DIS
0
EN
EN
1
I2CSTX
DMA I2C Slave TX
4
1
DIS
DIS
0
EN
EN
1
SINC2
SINC2 Output Step detection
11
1
DIS
DIS
0
EN
EN
1
SPI1RX
DMA SPI 1 RX
1
1
DIS
DIS
0
EN
EN
1
SPI1TX
DMA SPI 1 TX
0
1
DIS
DIS
0
EN
EN
1
UARTRX
DMA UART RX
3
1
DIS
DIS
0
EN
EN
1
UARTTX
DMA UART TX
2
1
DIS
DIS
0
EN
EN
1
DMACFG
Configuraton
0x4
32
read-write
n
0x0
0x0
ENABLE
Master DMA controller enable
0
1
DIS
DIS
0
EN
EN
1
DMAENCLR
Channel Enable Clear
0x2C
32
write-only
n
0x0
0x0
ADC0
ADC0
9
1
DIS
DIS
0
EN
EN
1
ADC1
ADC1
10
1
DIS
DIS
0
EN
EN
1
DAC
DAC DMA Output
8
1
DIS
DIS
0
EN
EN
1
I2CMRX
DMA I2C Master RX
7
1
DIS
DIS
0
EN
EN
1
I2CMTX
DMA I2C Master TX
6
1
DIS
DIS
0
EN
EN
1
I2CSRX
DMA I2C Slave RX
5
1
DIS
DIS
0
EN
EN
1
I2CSTX
DMA I2C Slave TX
4
1
DIS
DIS
0
EN
EN
1
SINC2
SINC2 Output Step detection
11
1
DIS
DIS
0
EN
EN
1
SPI1RX
DMA SPI 1 RX
1
1
DIS
DIS
0
EN
EN
1
SPI1TX
DMA SPI 1 TX
0
1
DIS
DIS
0
EN
EN
1
UARTRX
DMA UART RX
3
1
DIS
DIS
0
EN
EN
1
UARTTX
DMA UART TX
2
1
DIS
DIS
0
EN
EN
1
DMAENSET
Channel Enable Set
0x28
32
read-write
n
0x0
0x0
ADC0
ADC0
9
1
DIS
DIS
0
EN
EN
1
ADC1
ADC1
10
1
DIS
DIS
0
EN
EN
1
DAC
DAC DMA Output
8
1
DIS
DIS
0
EN
EN
1
I2CMRX
DMA I2C Master RX
7
1
DIS
DIS
0
EN
EN
1
I2CMTX
DMA I2C Master TX
6
1
DIS
DIS
0
EN
EN
1
I2CSRX
DMA I2C Slave RX
5
1
DIS
DIS
0
EN
EN
1
I2CSTX
DMA I2C Slave TX
4
1
DIS
DIS
0
EN
EN
1
SINC2
SINC2 Output Step detection
11
1
DIS
DIS
0
EN
EN
1
SPI1RX
DMA SPI 1 RX
1
1
DIS
DIS
0
EN
EN
1
SPI1TX
DMA SPI 1 TX
0
1
DIS
DIS
0
EN
EN
1
UARTRX
DMA UART RX
3
1
DIS
DIS
0
EN
EN
1
UARTTX
DMA UART TX
2
1
DIS
DIS
0
EN
EN
1
DMAERRCLR
Bus Error Clear
0x4C
32
read-write
n
0x0
0x0
ERROR
DMA Error status
0
1
DIS
DIS
0
EN
EN
1
DMAPCELLID0
PrimeCell identification 0
0xFF0
8
read-only
n
0x0
0x0
PCELLID0
Primecell Identification
0
8
DMAPCELLID1
PrimeCell identification 1
0xFF4
8
read-only
n
0x0
0x0
PCELLID1
Primecell Identification
0
8
DMAPCELLID2
PrimeCell identification 2
0xFF8
8
read-only
n
0x0
0x0
PCELLID2
Primecell Identification
0
8
DMAPCELLID3
PrimeCell identification 3
0xFFC
8
read-only
n
0x0
0x0
PCELLID3
Primecell Identification
0
8
DMAPDBPTR
Channel primary control database pointer
0x8
32
read-write
n
0x0
0x0
CTRLBASEPTR
Pointer to the base address of the primary data structure
0
32
DMAPERID0
Peripheral identification 0
0xFE0
8
read-only
n
0x0
0x0
PARTNO0
Identifies the peripheral (part_number_0)
0
8
DMAPERID1
Peripheral identification 1
0xFE4
8
read-only
n
0x0
0x0
JEP106ID0
JEP106 identity code [3:0]
4
4
PARTNO1
Identifies the peripheral (part_number_1)
0
4
DMAPERID2
Peripheral identification 2
0xFE8
8
read-only
n
0x0
0x0
JEDECUSED
This indicates that the controller uses a manufacturer?s identity code that was allocated by JEDEC according to JEP106.
3
1
DIS
DIS
0
EN
EN
1
JEP106ID1
JEP106 identity code [6:4].
0
3
REVISION
The revision status of the controller.
4
4
DMAPERID3
Peripheral identification 3
0xFEC
8
read-only
n
0x0
0x0
MODNUM
The customer must update this field if they modify the RTL of the controller.
0
4
DMAPERID4
Peripheral identification 4
0xFD0
8
read-only
n
0x0
0x0
BLOCKCOUNT
The number of 4KB address blocks you require, to access the registers, expressed in powers of 2.
4
4
JEP106CCODE
The JEP106 continuation code value represents how many 0x7F continuation characters occur in the manufacturer?s identity code.
0
4
DMAPRICLR
Channel Priority Clear
0x3C
32
write-only
n
0x0
0x0
ADC0
ADC0
9
1
DIS
DIS
0
EN
EN
1
ADC1
ADC1
10
1
DIS
DIS
0
EN
EN
1
DAC
DAC DMA Output
8
1
DIS
DIS
0
EN
EN
1
I2CMRX
DMA I2C Master RX
7
1
DIS
DIS
0
EN
EN
1
I2CMTX
DMA I2C Master TX
6
1
DIS
DIS
0
EN
EN
1
I2CSRX
DMA I2C Slave RX
5
1
DIS
DIS
0
EN
EN
1
I2CSTX
DMA I2C Slave TX
4
1
DIS
DIS
0
EN
EN
1
SINC2
SINC2 Output Step detection
11
1
DIS
DIS
0
EN
EN
1
SPI1RX
DMA SPI 1 RX
1
1
DIS
DIS
0
EN
EN
1
SPI1TX
DMA SPI 1 TX
0
1
DIS
DIS
0
EN
EN
1
UARTRX
DMA UART RX
3
1
DIS
DIS
0
EN
EN
1
UARTTX
DMA UART TX
2
1
DIS
DIS
0
EN
EN
1
DMAPRISET
Channel Priority Set
0x38
32
read-write
n
0x0
0x0
ADC0
ADC0
9
1
DIS
DIS
0
EN
EN
1
ADC1
ADC1
10
1
DIS
DIS
0
EN
EN
1
DAC
DAC DMA Output
8
1
DIS
DIS
0
EN
EN
1
I2CMRX
DMA I2C Master RX
7
1
DIS
DIS
0
EN
EN
1
I2CMTX
DMA I2C Master TX
6
1
DIS
DIS
0
EN
EN
1
I2CSRX
DMA I2C Slave RX
5
1
DIS
DIS
0
EN
EN
1
I2CSTX
DMA I2C Slave TX
4
1
DIS
DIS
0
EN
EN
1
SINC2
SINC2 Output Step detection
11
1
DIS
DIS
0
EN
EN
1
SPI1RX
DMA SPI 1 RX
1
1
DIS
DIS
0
EN
EN
1
SPI1TX
DMA SPI 1 TX
0
1
DIS
DIS
0
EN
EN
1
UARTRX
DMA UART RX
3
1
DIS
DIS
0
EN
EN
1
UARTTX
DMA UART TX
2
1
DIS
DIS
0
EN
EN
1
DMARMSKCLR
Channel Request Mask Clear
0x24
32
write-only
n
0x0
0x0
ADC0
ADC0
9
1
DIS
DIS
0
EN
EN
1
ADC1
ADC1
10
1
DIS
DIS
0
EN
EN
1
DAC
DAC DMA Output
8
1
DIS
DIS
0
EN
EN
1
I2CMRX
DMA I2C Master RX
7
1
DIS
DIS
0
EN
EN
1
I2CMTX
DMA I2C Master TX
6
1
DIS
DIS
0
EN
EN
1
I2CSRX
DMA I2C Slave RX
5
1
DIS
DIS
0
EN
EN
1
I2CSTX
DMA I2C Slave TX
4
1
DIS
DIS
0
EN
EN
1
SINC2
SINC2 Output Step detection
11
1
DIS
DIS
0
EN
EN
1
SPI1RX
DMA SPI 1 RX
1
1
DIS
DIS
0
EN
EN
1
SPI1TX
DMA SPI 1 TX
0
1
DIS
DIS
0
EN
EN
1
UARTRX
DMA UART RX
3
1
DIS
DIS
0
EN
EN
1
UARTTX
DMA UART TX
2
1
DIS
DIS
0
EN
EN
1
DMARMSKSET
Channel Request Mask Set
0x20
32
read-write
n
0x0
0x0
ADC0
ADC0
9
1
DIS
DIS
0
EN
EN
1
ADC1
ADC1
10
1
DIS
DIS
0
EN
EN
1
DAC
DAC DMA Output
8
1
DIS
DIS
0
EN
EN
1
I2CMRX
DMA I2C Master RX
7
1
DIS
DIS
0
EN
EN
1
I2CMTX
DMA I2C Master TX
6
1
DIS
DIS
0
EN
EN
1
I2CSRX
DMA I2C Slave RX
5
1
DIS
DIS
0
EN
EN
1
I2CSTX
DMA I2C Slave TX
4
1
DIS
DIS
0
EN
EN
1
SINC2
SINC2 Output Step detection
11
1
DIS
DIS
0
EN
EN
1
SPI1RX
DMA SPI 1 RX
1
1
DIS
DIS
0
EN
EN
1
SPI1TX
DMA SPI 1 TX
0
1
DIS
DIS
0
EN
EN
1
UARTRX
DMA UART RX
3
1
DIS
DIS
0
EN
EN
1
UARTTX
DMA UART TX
2
1
DIS
DIS
0
EN
EN
1
DMASTA
Returns the status of the controller when not in the reset state.
0x0
32
read-only
n
0x0
0x0
CHNLSMINUS1
Number of available DMA channels minus one.
16
5
TWELVECHNLS
- Controller configured to use 12 DMA channels
11
FOURTEENCHNLS
- Controller configured to use 14 DMA channels
13
ENABLE
Master DMA controller enable status.
0
1
CLR
CLR
0
SET
SET
1
STATE
Current state of the control state machine.
4
4
IDLE
- Idle
0
RDCHNLDATA
- Reading channel controller data
1
SCATRGATHR
- Peripheral scatter-gather transition
10
RDSRCENDPTR
- Reading source data end pointer
2
RDDSTENDPTR
- Reading destination data end pointer
3
RDSRCDATA
- Reading source data
4
WRDSTDATA
- Writing destination data
5
WAITDMAREQCLR
- Waiting for DMA request to clear
6
WRCHNLDATA
- Writing channel controller data
7
STALLED
- Stalled
8
DONE
- Done
9
DMASWREQ
Channel Software Request
0x14
32
write-only
n
0x0
0x0
ADC0
ADC0
9
1
DIS
DIS
0
EN
EN
1
ADC1
ADC1
10
1
DIS
DIS
0
EN
EN
1
DAC
DAC DMA Output
8
1
DIS
DIS
0
EN
EN
1
I2CMRX
DMA I2C Master RX
7
1
DIS
DIS
0
EN
EN
1
I2CMTX
DMA I2C Master TX
6
1
DIS
DIS
0
EN
EN
1
I2CSRX
DMA I2C Slave RX
5
1
DIS
DIS
0
EN
EN
1
I2CSTX
DMA I2C Slave TX
4
1
DIS
DIS
0
EN
EN
1
SINC2
SINC2 Output Step detection
11
1
DIS
DIS
0
EN
EN
1
SPI1RX
DMA SPI 1 RX
1
1
DIS
DIS
0
EN
EN
1
SPI1TX
DMA SPI 1 TX
0
1
DIS
DIS
0
EN
EN
1
UARTRX
DMA UART RX
3
1
DIS
DIS
0
EN
EN
1
UARTTX
DMA UART TX
2
1
DIS
DIS
0
EN
EN
1
ADI_FEE
Flash Controller
FEE
0x0
0x0
0x84
registers
n
SINC2
15
FLASH
16
FEEADR0H
Low Page (Upper 16 bits)
0x14
16
read-write
n
0x0
0x0
VALUE
Value
0
2
FEEADR0L
Low Page (Lower 16 bits)
0x10
16
read-write
n
0x0
0x0
VALUE
Value
0
16
FEEADR1H
Hi Page (Upper 16 bits)
0x1C
16
read-write
n
0x0
0x0
VALUE
Value
0
2
FEEADR1L
Hi Page (Lower 16 bits)
0x18
16
read-write
n
0x0
0x0
VALUE
Value
0
16
FEEADRAH
Abort address (Upper 16 bits)
0x4C
16
read-only
n
0x0
0x0
VALUE
Value
0
16
FEEADRAL
Abort address (Lower 16 bits)
0x48
16
read-only
n
0x0
0x0
VALUE
Value
0
16
FEEAEN0
Lower 16 bits of the sys irq abort enable register.
0x78
16
read-write
n
0x0
0x0
ADC0
TBD
13
1
DIS
DIS
0
EN
EN
1
ADC1
TBD
14
1
DIS
DIS
0
EN
EN
1
EXTINT0
TBD
1
1
DIS
DIS
0
EN
EN
1
EXTINT1
TBD
2
1
DIS
DIS
0
EN
EN
1
EXTINT2
TBD
3
1
DIS
DIS
0
EN
EN
1
EXTINT3
TBD
4
1
DIS
DIS
0
EN
EN
1
EXTINT4
TBD
5
1
DIS
DIS
0
EN
EN
1
EXTINT5
TBD
6
1
DIS
DIS
0
EN
EN
1
EXTINT6
TBD
7
1
DIS
DIS
0
EN
EN
1
EXTINT7
TBD
8
1
DIS
DIS
0
EN
EN
1
SINC2
TBD
15
1
DIS
DIS
0
EN
EN
1
T0
TBD
11
1
DIS
DIS
0
EN
EN
1
T1
TBD
12
1
DIS
DIS
0
EN
EN
1
T2
TBD
0
1
DIS
DIS
0
EN
EN
1
T3
TBD
9
1
DIS
DIS
0
EN
EN
1
FEEAEN1
Upper 16 bits of the sys irq abort enable register.
0x7C
16
read-write
n
0x0
0x0
DMADAC
TBD
15
1
DIS
DIS
0
EN
EN
1
DMAERROR
TBD
6
1
DIS
DIS
0
EN
EN
1
DMAI2CMRX
TBD
14
1
DIS
DIS
0
EN
EN
1
DMAI2CMTX
TBD
13
1
DIS
DIS
0
EN
EN
1
DMAI2CSRX
TBD
12
1
DIS
DIS
0
EN
EN
1
DMAI2CSTX
TBD
11
1
DIS
DIS
0
EN
EN
1
DMASPI1RX
TBD
8
1
DIS
DIS
0
EN
EN
1
DMASPI1TX
TBD
7
1
DIS
DIS
0
EN
EN
1
DMAUARTRX
TBD
10
1
DIS
DIS
0
EN
EN
1
DMAUARTTX
TBD
9
1
DIS
DIS
0
EN
EN
1
FEE
TBD
0
1
DIS
DIS
0
EN
EN
1
I2CM
TBD
5
1
DIS
DIS
0
EN
EN
1
I2CS
TBD
4
1
DIS
DIS
0
EN
EN
1
SPI0
TBD
2
1
DIS
DIS
0
EN
EN
1
SPI1
TBD
3
1
DIS
DIS
0
EN
EN
1
UART
TBD
1
1
DIS
DIS
0
EN
EN
1
FEEAEN2
Upper 32..47 bits of the sys irq abort enable register.
0x80
16
read-write
n
0x0
0x0
DMAADC0
TBD
0
1
DIS
DIS
0
EN
EN
1
DMAADC1
TBD
1
1
DIS
DIS
0
EN
EN
1
DMASINC2
TBD
2
1
DIS
DIS
0
EN
EN
1
PWM0
TBD
4
1
DIS
DIS
0
EN
EN
1
PWM1
TBD
5
1
DIS
DIS
0
EN
EN
1
PWM2
TBD
6
1
DIS
DIS
0
EN
EN
1
PWMTRIP
TBD
3
1
DIS
DIS
0
EN
EN
1
FEECMD
Command register
0x8
16
read-write
n
0x0
0x0
CMD
Command
0
4
IDLE
- No command executed
0
ERASEPAGE
- Erase Page
1
SIGN
- Sign Range
2
MASSERASE
- Mass Erase User Space
3
ABORT
- Abort a running command
4
FEECON0
Command Control Register
0x4
16
read-write
n
0x0
0x0
IENCMD
Command complete interrupt enable
0
1
DIS
DIS
0
EN
EN
1
IENERR
Error interrupt enable
1
1
DIS
DIS
0
EN
EN
1
WREN
Write enable.
2
1
DIS
DIS
0
EN
EN
1
FEECON1
User Setup register
0x38
16
read-write
n
0x0
0x0
DBG
Serial Wire debug enable ,
0
1
DIS
DIS
0
EN
EN
1
FEEKEY
Key
0x20
16
write-only
n
0x0
0x0
VALUE
Value
0
16
USERKEY2
USERKEY2
61731
USERKEY1
USERKEY1
62550
FEEPROH
Write Protection (Upper 16 bits)
0x2C
16
read-write
n
0x0
0x0
VALUE
Value
0
16
FEEPROL
Write Protection (Lower 16 bits)
0x28
16
read-write
n
0x0
0x0
VALUE
Value
0
16
FEESIGH
Signature (Upper 16 bits)
0x34
16
read-only
n
0x0
0x0
VALUE
Value
0
8
FEESIGL
Signature (Lower 16 bits)
0x30
16
read-only
n
0x0
0x0
VALUE
Value
0
16
FEESTA
Status Register
0x0
16
read-only
n
0x0
0x0
CMDBUSY
Command busy
0
1
CLR
CLR
0
SET
SET
1
CMDDONE
Command complete
2
1
CLR
CLR
0
SET
SET
1
CMDRES
Command result
4
2
SUCCESS
SUCCESS
0
PROTECTED
PROTECTED
1
VERIFYERR
VERIFYERR
2
ABORT
ABORT
3
SIGNERR
Info space signature check on reset error
6
1
CLR
CLR
0
SET
SET
1
WRBUSY
Write busy
1
1
CLR
CLR
0
SET
SET
1
WRDONE
Write Complete
3
1
CLR
CLR
0
SET
SET
1
ADI_GPIO0
General Purpose Input Output
GPIO
0x0
0x0
0x28
registers
n
GP0CLR
GPIO Port 0 data out clear.
0x20
8
write-only
n
0x0
0x0
CLR0
Set Output Low for port pin
0
1
CLR
CLR
1
CLR1
Set Output Low for port pin
1
1
CLR
CLR
1
CLR2
Set Output Low for port pin
2
1
CLR
CLR
1
CLR3
Set Output Low for port pin
3
1
CLR
CLR
1
CLR4
Set Output Low for port pin
4
1
CLR
CLR
1
CLR5
Set Output Low for port pin
5
1
CLR
CLR
1
CLR6
Set Output Low for port pin
6
1
CLR
CLR
1
CLR7
Set Output Low for port pin
7
1
CLR
CLR
1
GP0CON
GPIO Port 0 configuration
0x0
16
read-write
n
0x0
0x0
CON0
Configuration bits for P0.0
0
2
GPIO
GPIO
0
SPI1MISO
SPI1MISO
1
CON1
Configuration bits for P0.1
2
2
GPIO
GPIO
0
SPI1SCLK
SPI1SCLK
1
I2CSCL
I2CSCL
2
UARTRXD
UARTRXD
3
CON2
Configuration bits for P0.2
4
2
GPIO
GPIO
0
SPI1MOSI
SPI1MOSI
1
I2CSDA
I2CSDA
2
UARTTXD
UARTTXD
3
CON3
Configuration bits for P0.3
6
2
GPIOIRQ0
GPIOIRQ0
0
SPI1CS0
SPI1CS0
1
CON4
Configuration bits for P0.4
8
2
GPIO
GPIO
0
UARTRTS
UARTRTS
1
ECLKOUT
ECLKOUT
2
CON5
Configuration bits for P0.5
10
2
GPIOIRQ1
GPIOIRQ1
0
UARTCTS
UARTCTS
1
CON6
Configuration bits for P0.6
12
2
GPIOIRQ2
GPIOIRQ2
0
UARTRXD
UARTRXD
1
CON7
Configuration bits for P0.7
14
2
PORB
PORB
0
GPIO
GPIO
1
UARTTXD
UARTTXD
2
GP0IN
GPIO Port 0 data input.
0x14
8
read-only
n
0x0
0x0
IN0
Input for port pin
0
1
LOW
LOW
0
HIGH
HIGH
1
IN1
Input for port pin
1
1
LOW
LOW
0
HIGH
HIGH
1
IN2
Input for port pin
2
1
LOW
LOW
0
HIGH
HIGH
1
IN3
Input for port pin
3
1
LOW
LOW
0
HIGH
HIGH
1
IN4
Input for port pin
4
1
LOW
LOW
0
HIGH
HIGH
1
IN5
Input for port pin
5
1
LOW
LOW
0
HIGH
HIGH
1
IN6
Input for port pin
6
1
LOW
LOW
0
HIGH
HIGH
1
IN7
Input for port pin
7
1
LOW
LOW
0
HIGH
HIGH
1
GP0OCE
GPIO Port 0 tri state
0xC
8
read-write
n
0x0
0x0
OCE0
open circuit Enable for port pin
0
1
DIS
DIS
0
EN
EN
1
OCE1
open circuit Enable for port pin
1
1
DIS
DIS
0
EN
EN
1
OCE2
open circuit Enable for port pin
2
1
DIS
DIS
0
EN
EN
1
OCE3
open circuit Enable for port pin
3
1
DIS
DIS
0
EN
EN
1
OCE4
open circuit Enable for port pin
4
1
DIS
DIS
0
EN
EN
1
OCE5
open circuit Enable for port pin
5
1
DIS
DIS
0
EN
EN
1
OCE6
open circuit Enable for port pin
6
1
DIS
DIS
0
EN
EN
1
OCE7
open circuit Enable for port pin
7
1
DIS
DIS
0
EN
EN
1
GP0OEN
GPIO Port 0 output enable
0x4
8
read-write
n
0x0
0x0
OEN0
Direction for port pin
0
1
IN
IN
0
OUT
OUT
1
OEN1
Direction for port pin
1
1
IN
IN
0
OUT
OUT
1
OEN2
Direction for port pin
2
1
IN
IN
0
OUT
OUT
1
OEN3
Direction for port pin
3
1
IN
IN
0
OUT
OUT
1
OEN4
Direction for port pin
4
1
IN
IN
0
OUT
OUT
1
OEN5
Direction for port pin
5
1
IN
IN
0
OUT
OUT
1
OEN6
Direction for port pin
6
1
IN
IN
0
OUT
OUT
1
OEN7
Direction for port pin
7
1
IN
IN
0
OUT
OUT
1
GP0OUT
GPIO Port 0 data out.
0x18
8
read-write
n
0x0
0x0
OUT0
Output for port pin
0
1
LOW
LOW
0
HIGH
HIGH
1
OUT1
Output for port pin
1
1
LOW
LOW
0
HIGH
HIGH
1
OUT2
Output for port pin
2
1
LOW
LOW
0
HIGH
HIGH
1
OUT3
Output for port pin
3
1
LOW
LOW
0
HIGH
HIGH
1
OUT4
Output for port pin
4
1
LOW
LOW
0
HIGH
HIGH
1
OUT5
Output for port pin
5
1
LOW
LOW
0
HIGH
HIGH
1
OUT6
Output for port pin
6
1
LOW
LOW
0
HIGH
HIGH
1
OUT7
Output for port pin
7
1
LOW
LOW
0
HIGH
HIGH
1
GP0PUL
GPIO Port 0 output pull up enable.
0x8
8
read-write
n
0x0
0x0
PUL0
Pull Up Enable for port pin
0
1
DIS
DIS
0
EN
EN
1
PUL1
Pull Up Enable for port pin
1
1
DIS
DIS
0
EN
EN
1
PUL2
Pull Up Enable for port pin
2
1
DIS
DIS
0
EN
EN
1
PUL3
Pull Up Enable for port pin
3
1
DIS
DIS
0
EN
EN
1
PUL4
Pull Up Enable for port pin
4
1
DIS
DIS
0
EN
EN
1
PUL5
Pull Up Enable for port pin
5
1
DIS
DIS
0
EN
EN
1
PUL6
Pull Up Enable for port pin
6
1
DIS
DIS
0
EN
EN
1
PUL7
Pull Up Enable for port pin
7
1
DIS
DIS
0
EN
EN
1
GP0SET
GPIO Port 0 data out set
0x1C
8
write-only
n
0x0
0x0
SET0
Set Output High for port pin
0
1
SET
SET
1
SET1
Set Output High for port pin
1
1
SET
SET
1
SET2
Set Output High for port pin
2
1
SET
SET
1
SET3
Set Output High for port pin
3
1
SET
SET
1
SET4
Set Output High for port pin
4
1
SET
SET
1
SET5
Set Output High for port pin
5
1
SET
SET
1
SET6
Set Output High for port pin
6
1
SET
SET
1
SET7
Set Output High for port pin
7
1
SET
SET
1
GP0TGL
GPIO Port 0 pin toggle.
0x24
8
write-only
n
0x0
0x0
TGL0
Toggle Output for port pin
0
1
TGL
TGL
1
TGL1
Toggle Output for port pin
1
1
TGL
TGL
1
TGL2
Toggle Output for port pin
2
1
TGL
TGL
1
TGL3
Toggle Output for port pin
3
1
TGL
TGL
1
TGL4
Toggle Output for port pin
4
1
TGL
TGL
1
TGL5
Toggle Output for port pin
5
1
TGL
TGL
1
TGL6
Toggle Output for port pin
6
1
TGL
TGL
1
TGL7
Toggle Output for port pin
7
1
TGL
TGL
1
ADI_GPIO1
General Purpose Input Output
GPIO
0x0
0x0
0x28
registers
n
GP1CLR
GPIO Port 1 data out clear.
0x20
8
write-only
n
0x0
0x0
CLR0
Set Output Low for port pin
0
1
CLR
CLR
1
CLR1
Set Output Low for port pin
1
1
CLR
CLR
1
CLR2
Set Output Low for port pin
2
1
CLR
CLR
1
CLR3
Set Output Low for port pin
3
1
CLR
CLR
1
CLR4
Set Output Low for port pin
4
1
CLR
CLR
1
CLR5
Set Output Low for port pin
5
1
CLR
CLR
1
CLR6
Set Output Low for port pin
6
1
CLR
CLR
1
CLR7
Set Output Low for port pin
7
1
CLR
CLR
1
GP1CON
GPIO Port 1 configuration
0x0
16
read-write
n
0x0
0x0
CON0
Configuration bits for P1.0
0
2
GPIOIRQ3
GPIOIRQ3
0
PWMSYNC
PWMSYNC
1
EXTCLKIN
EXTCLKIN
2
CON1
Configuration bits for P1.1
2
2
GPIOIRQ4
GPIOIRQ4
0
PWMTRIP
PWMTRIP
1
CON2
Configuration bits for P1.2
4
2
GPIO
GPIO
0
PWM0
PWM0
1
CON3
Configuration bits for P1.3
6
2
GPIO
GPIO
0
PWM1
PWM1
1
CON4
Configuration bits for P1.4
8
2
GPIO
GPIO
0
PWM2
PWM2
1
SPI0MISO
SPI0MISO
2
CON5
Configuration bits for P1.5
10
2
GPIOIRQ5
GPIOIRQ5
0
PWM3
PWM3
1
SPI0SCLK
SPI0SCLK
2
CON6
Configuration bits for P1.6
12
2
GPIOIRQ6
GPIOIRQ6
0
PWM4
PWM4
1
SPI0MOSI
SPI0MOSI
2
CON7
Configuration bits for P1.7
14
2
GPIOIRQ7
GPIOIRQ7
0
PWM5
PWM5
1
SPI0CS
SPI0CS
2
GP1IN
GPIO Port 1 data input.
0x14
8
read-only
n
0x0
0x0
IN0
Input for port pin
0
1
LOW
LOW
0
HIGH
HIGH
1
IN1
Input for port pin
1
1
LOW
LOW
0
HIGH
HIGH
1
IN2
Input for port pin
2
1
LOW
LOW
0
HIGH
HIGH
1
IN3
Input for port pin
3
1
LOW
LOW
0
HIGH
HIGH
1
IN4
Input for port pin
4
1
LOW
LOW
0
HIGH
HIGH
1
IN5
Input for port pin
5
1
LOW
LOW
0
HIGH
HIGH
1
IN6
Input for port pin
6
1
LOW
LOW
0
HIGH
HIGH
1
IN7
Input for port pin
7
1
LOW
LOW
0
HIGH
HIGH
1
GP1OCE
GPIO Port 1 tri state
0xC
8
read-write
n
0x0
0x0
OCE0
open circuit Enable for port pin
0
1
DIS
DIS
0
EN
EN
1
OCE1
open circuit Enable for port pin
1
1
DIS
DIS
0
EN
EN
1
OCE2
open circuit Enable for port pin
2
1
DIS
DIS
0
EN
EN
1
OCE3
open circuit Enable for port pin
3
1
DIS
DIS
0
EN
EN
1
OCE4
open circuit Enable for port pin
4
1
DIS
DIS
0
EN
EN
1
OCE5
open circuit Enable for port pin
5
1
DIS
DIS
0
EN
EN
1
OCE6
open circuit Enable for port pin
6
1
DIS
DIS
0
EN
EN
1
OCE7
open circuit Enable for port pin
7
1
DIS
DIS
0
EN
EN
1
GP1OEN
GPIO Port 1 output enable
0x4
8
read-write
n
0x0
0x0
OEN0
Direction for port pin
0
1
IN
IN
0
OUT
OUT
1
OEN1
Direction for port pin
1
1
IN
IN
0
OUT
OUT
1
OEN2
Direction for port pin
2
1
IN
IN
0
OUT
OUT
1
OEN3
Direction for port pin
3
1
IN
IN
0
OUT
OUT
1
OEN4
Direction for port pin
4
1
IN
IN
0
OUT
OUT
1
OEN5
Direction for port pin
5
1
IN
IN
0
OUT
OUT
1
OEN6
Direction for port pin
6
1
IN
IN
0
OUT
OUT
1
OEN7
Direction for port pin
7
1
IN
IN
0
OUT
OUT
1
GP1OUT
GPIO Port 1 data out.
0x18
8
read-write
n
0x0
0x0
OUT0
Output for port pin
0
1
LOW
LOW
0
HIGH
HIGH
1
OUT1
Output for port pin
1
1
LOW
LOW
0
HIGH
HIGH
1
OUT2
Output for port pin
2
1
LOW
LOW
0
HIGH
HIGH
1
OUT3
Output for port pin
3
1
LOW
LOW
0
HIGH
HIGH
1
OUT4
Output for port pin
4
1
LOW
LOW
0
HIGH
HIGH
1
OUT5
Output for port pin
5
1
LOW
LOW
0
HIGH
HIGH
1
OUT6
Output for port pin
6
1
LOW
LOW
0
HIGH
HIGH
1
OUT7
Output for port pin
7
1
LOW
LOW
0
HIGH
HIGH
1
GP1PUL
GPIO Port 1 output pull up enable.
0x8
8
read-write
n
0x0
0x0
PUL0
Pull Up Enable for port pin
0
1
DIS
DIS
0
EN
EN
1
PUL1
Pull Up Enable for port pin
1
1
DIS
DIS
0
EN
EN
1
PUL2
Pull Up Enable for port pin
2
1
DIS
DIS
0
EN
EN
1
PUL3
Pull Up Enable for port pin
3
1
DIS
DIS
0
EN
EN
1
PUL4
Pull Up Enable for port pin
4
1
DIS
DIS
0
EN
EN
1
PUL5
Pull Up Enable for port pin
5
1
DIS
DIS
0
EN
EN
1
PUL6
Pull Up Enable for port pin
6
1
DIS
DIS
0
EN
EN
1
PUL7
Pull Up Enable for port pin
7
1
DIS
DIS
0
EN
EN
1
GP1SET
GPIO Port 1 data out set
0x1C
8
write-only
n
0x0
0x0
SET0
Set Output High for port pin
0
1
SET
SET
1
SET1
Set Output High for port pin
1
1
SET
SET
1
SET2
Set Output High for port pin
2
1
SET
SET
1
SET3
Set Output High for port pin
3
1
SET
SET
1
SET4
Set Output High for port pin
4
1
SET
SET
1
SET5
Set Output High for port pin
5
1
SET
SET
1
SET6
Set Output High for port pin
6
1
SET
SET
1
SET7
Set Output High for port pin
7
1
SET
SET
1
GP1TGL
GPIO Port 1 pin toggle.
0x24
8
write-only
n
0x0
0x0
TGL0
Toggle Output for port pin
0
1
TGL
TGL
1
TGL1
Toggle Output for port pin
1
1
TGL
TGL
1
TGL2
Toggle Output for port pin
2
1
TGL
TGL
1
TGL3
Toggle Output for port pin
3
1
TGL
TGL
1
TGL4
Toggle Output for port pin
4
1
TGL
TGL
1
TGL5
Toggle Output for port pin
5
1
TGL
TGL
1
TGL6
Toggle Output for port pin
6
1
TGL
TGL
1
TGL7
Toggle Output for port pin
7
1
TGL
TGL
1
ADI_GPIO2
General Purpose Input Output
GPIO
0x0
0x0
0x28
registers
n
GP2CLR
GPIO Port 2 data out clear.
0x20
8
write-only
n
0x0
0x0
CLR0
Set Output Low for port pin
0
1
CLR
CLR
1
CLR1
Set Output Low for port pin
1
1
CLR
CLR
1
CLR2
Set Output Low for port pin
2
1
CLR
CLR
1
CLR3
Set Output Low for port pin
3
1
CLR
CLR
1
CLR4
Set Output Low for port pin
4
1
CLR
CLR
1
CLR5
Set Output Low for port pin
5
1
CLR
CLR
1
CLR6
Set Output Low for port pin
6
1
CLR
CLR
1
CLR7
Set Output Low for port pin
7
1
CLR
CLR
1
GP2CON
GPIO Port 2 configuration
0x0
16
read-write
n
0x0
0x0
CON0
Configuration bits for P2.0
0
2
GPIO
GPIO
0
I2CSCL
I2CSCL
1
CON1
Configuration bits for P2.1
2
2
GPIO
GPIO
0
I2CSDA
I2CSDA
1
CON2
Configuration bits for P2.2
4
2
GPIO
GPIO
0
CON3
Configuration bits for P2.3
6
2
SWCLK
SWCLK
1
CON4
Configuration bits for P2.4
8
2
SWDATA
SWDATA
1
GP2IN
GPIO Port 2 data input.
0x14
8
read-only
n
0x0
0x0
IN0
Input for port pin
0
1
LOW
LOW
0
HIGH
HIGH
1
IN1
Input for port pin
1
1
LOW
LOW
0
HIGH
HIGH
1
IN2
Input for port pin
2
1
LOW
LOW
0
HIGH
HIGH
1
IN3
Input for port pin
3
1
LOW
LOW
0
HIGH
HIGH
1
IN4
Input for port pin
4
1
LOW
LOW
0
HIGH
HIGH
1
IN5
Input for port pin
5
1
LOW
LOW
0
HIGH
HIGH
1
IN6
Input for port pin
6
1
LOW
LOW
0
HIGH
HIGH
1
IN7
Input for port pin
7
1
LOW
LOW
0
HIGH
HIGH
1
GP2OCE
GPIO Port 2 tri state
0xC
8
read-write
n
0x0
0x0
OCE0
open circuit Enable for port pin
0
1
DIS
DIS
0
EN
EN
1
OCE1
open circuit Enable for port pin
1
1
DIS
DIS
0
EN
EN
1
OCE2
open circuit Enable for port pin
2
1
DIS
DIS
0
EN
EN
1
OCE3
open circuit Enable for port pin
3
1
DIS
DIS
0
EN
EN
1
OCE4
open circuit Enable for port pin
4
1
DIS
DIS
0
EN
EN
1
OCE5
open circuit Enable for port pin
5
1
DIS
DIS
0
EN
EN
1
OCE6
open circuit Enable for port pin
6
1
DIS
DIS
0
EN
EN
1
OCE7
open circuit Enable for port pin
7
1
DIS
DIS
0
EN
EN
1
GP2OEN
GPIO Port 2 output enable
0x4
8
read-write
n
0x0
0x0
OEN0
Direction for port pin
0
1
IN
IN
0
OUT
OUT
1
OEN1
Direction for port pin
1
1
IN
IN
0
OUT
OUT
1
OEN2
Direction for port pin
2
1
IN
IN
0
OUT
OUT
1
OEN3
Direction for port pin
3
1
IN
IN
0
OUT
OUT
1
OEN4
Direction for port pin
4
1
IN
IN
0
OUT
OUT
1
OEN5
Direction for port pin
5
1
IN
IN
0
OUT
OUT
1
OEN6
Direction for port pin
6
1
IN
IN
0
OUT
OUT
1
OEN7
Direction for port pin
7
1
IN
IN
0
OUT
OUT
1
GP2OUT
GPIO Port 2 data out.
0x18
8
read-write
n
0x0
0x0
OUT0
Output for port pin
0
1
LOW
LOW
0
HIGH
None
1
OUT1
Output for port pin
1
1
LOW
LOW
0
HIGH
HIGH
1
OUT2
Output for port pin
2
1
LOW
LOW
0
HIGH
HIGH
1
OUT3
Output for port pin
3
1
LOW
LOW
0
HIGH
HIGH
1
OUT4
Output for port pin
4
1
LOW
LOW
0
HIGH
HIGH
1
OUT5
Output for port pin
5
1
LOW
LOW
0
HIGH
HIGH
1
OUT6
Output for port pin
6
1
LOW
LOW
0
HIGH
HIGH
1
OUT7
Output for port pin
7
1
LOW
LOW
0
HIGH
HIGH
1
GP2PUL
GPIO Port 2 output pull up enable.
0x8
8
read-write
n
0x0
0x0
PUL0
Pull Up Enable for port pin
0
1
DIS
DIS
0
EN
EN
1
PUL1
Pull Up Enable for port pin
1
1
DIS
DIS
0
EN
EN
1
PUL2
Pull Up Enable for port pin
2
1
DIS
DIS
0
EN
EN
1
PUL3
Pull Up Enable for port pin
3
1
DIS
DIS
0
EN
EN
1
PUL4
Pull Up Enable for port pin
4
1
DIS
DIS
0
EN
EN
1
PUL5
Pull Up Enable for port pin
5
1
DIS
DIS
0
EN
EN
1
PUL6
Pull Up Enable for port pin
6
1
DIS
DIS
0
EN
EN
1
PUL7
Pull Up Enable for port pin
7
1
DIS
DIS
0
EN
EN
1
GP2SET
GPIO Port 2 data out set
0x1C
8
write-only
n
0x0
0x0
SET0
Set Output High for port pin
0
1
SET
SET
1
SET1
Set Output High for port pin
1
1
SET
SET
1
SET2
Set Output High for port pin
2
1
SET
SET
1
SET3
Set Output High for port pin
3
1
SET
SET
1
SET4
Set Output High for port pin
4
1
SET
SET
1
SET5
Set Output High for port pin
5
1
SET
SET
1
SET6
Set Output High for port pin
6
1
SET
SET
1
SET7
Set Output High for port pin
7
1
SET
SET
1
GP2TGL
GPIO Port 2 pin toggle.
0x24
8
write-only
n
0x0
0x0
TGL0
Toggle Output for port pin
0
1
TGL
TGL
1
TGL1
Toggle Output for port pin
1
1
TGL
TGL
1
TGL2
Toggle Output for port pin
2
1
TGL
TGL
1
TGL3
Toggle Output for port pin
3
1
TGL
TGL
1
TGL4
Toggle Output for port pin
4
1
TGL
TGL
1
TGL5
Toggle Output for port pin
5
1
TGL
TGL
1
TGL6
Toggle Output for port pin
6
1
TGL
TGL
1
TGL7
Toggle Output for port pin
7
1
TGL
TGL
1
ADI_I2C
I2C
I2C
0x0
0x0
0x54
registers
n
I2CS
20
I2CM
21
I2CADR0
1st Master Address Byte
0x18
8
read-write
n
0x0
0x0
VALUE
Address byte
0
8
I2CADR1
2nd Master Address Byte
0x1C
8
read-write
n
0x0
0x0
VALUE
Address byte
0
8
I2CALT
Hardware General Call ID
0x38
16
read-write
n
0x0
0x0
VALUE
Alt register
0
8
I2CDIV
Serial clock period divisor register
0x24
16
read-write
n
0x0
0x0
HIGH
High Time
8
8
LOW
Low Time
0
8
I2CFSTA
Master and Slave Rx/Tx FIFO Status Register
0x4C
16
read-write
n
0x0
0x0
MFLUSH
Flush the master transmit FIFO
9
1
DIS
DIS
0
EN
EN
1
MRXFSTA
Master receive FIFO Status
6
2
EMPTY
EMPTY
0
ONEBYTE
ONEBYTE
1
TWOBYTES
TWOBYTES
2
MTXFSTA
Master Transmit FIFO Status
4
2
EMPTY
EMPTY
0
ONEBYTE
ONEBYTE
1
TWOBYTES
TWOBYTES
2
SFLUSH
Flush the slave transmit FIFO
8
1
DIS
DIS
0
EN
EN
1
SRXFSTA
Slave receive FIFO Status
2
2
EMPTY
EMPTY
0
ONEBYTE
ONEBYTE
1
TWOBYTES
TWOBYTES
2
STXFSTA
Slave Transmit FIFO Status
0
2
EMPTY
EMPTY
0
ONEBYTE
ONEBYTE
1
TWOBYTES
TWOBYTES
2
I2CID0
1st Slave Address Device ID
0x3C
16
read-write
n
0x0
0x0
VALUE
Slave ID
0
8
I2CID1
2nd Slave Address Device ID
0x40
16
read-write
n
0x0
0x0
VALUE
Slave ID
0
8
I2CID2
3rd Slave Address Device ID
0x44
16
read-write
n
0x0
0x0
VALUE
Slave ID
0
8
I2CID3
4th Slave Address Device ID
0x48
16
read-write
n
0x0
0x0
VALUE
Slave ID
0
8
I2CMCON
Master Control Register
0x0
16
read-write
n
0x0
0x0
COMPETE
Compete for ownership
1
1
DIS
DIS
0
EN
EN
1
IENALOST
Arbitration lost interrupt enable
6
1
DIS
DIS
0
EN
EN
1
IENCMP
Transaction completed interrupt enable
8
1
DIS
DIS
0
EN
EN
1
IENNACK
ACK not received interrupt enable
7
1
DIS
DIS
0
EN
EN
1
IENRX
Receive request interrupt enable
4
1
DIS
DIS
0
EN
EN
1
IENTX
Transmit request interrupt enable
5
1
DIS
DIS
0
EN
EN
1
LOOPBACK
Internal loop back
2
1
DIS
DIS
0
EN
EN
1
MAS
Master Enable
0
1
DIS
DIS
0
EN
EN
1
RXDMA
Enable master Rx DMA request
10
1
DIS
DIS
0
EN
EN
1
STRETCH
Stretch SCL
3
1
DIS
DIS
0
EN
EN
1
TXDMA
Enable master Tx DMA request
11
1
DIS
DIS
0
EN
EN
1
I2CMCRXCNT
Master Current Receive Data Count
0x14
16
read-only
n
0x0
0x0
VALUE
Current Receive count
0
8
I2CMRX
Master Receive Data
0x8
8
read-only
n
0x0
0x0
VALUE
Current Receive Value
0
8
I2CMRXCNT
Master Receive Data Count
0x10
16
read-write
n
0x0
0x0
COUNT
Receive count
0
8
EXTEND
Extended Read
8
1
DIS
DIS
0
EN
EN
1
I2CMSTA
Master Status Register
0x4
16
read-only
n
0x0
0x0
ALOST
Arbitration lost
5
1
CLR
CLR
0
SET
SET
1
BUSY
Master Busy
6
1
CLR
CLR
0
SET
SET
1
LINEBUSY
Line is busy
10
1
CLR
CLR
0
SET
SET
1
MSTOP
STOP driven by th eI2C master
11
1
CLR
CLR
0
SET
SET
1
NACKADDR
Ack not received in response to an address
4
1
CLR
CLR
0
SET
SET
1
NACKDATA
Ack not received in response to data write
7
1
CLR
CLR
0
SET
SET
1
RXOF
Receive FIFO overflow
9
1
CLR
CLR
0
SET
SET
1
RXREQ
Receive request
3
1
CLR
CLR
0
SET
SET
1
TCOMP
Transaction completed
8
1
CLR
CLR
0
SET
SET
1
TXFSTA
Transmit FIFO Status
0
2
EMPTY
EMPTY
0
ONEBYTE
ONEBYTE
1
FULL
FULL
3
TXREQ
Transmit request
2
1
CLR
CLR
0
SET
SET
1
TXUR
Master Transmit FIFO underflow
12
1
CLR
CLR
0
SET
SET
1
I2CMTX
Master Transmit Data
0xC
8
write-only
n
0x0
0x0
VALUE
Current Transmit Value
0
8
I2CSCON
Slave Control Register
0x28
16
read-write
n
0x0
0x0
ADR10
Enable 10 bit addressing
1
1
DIS
DIS
0
EN
EN
1
EARLYTXR
Early transmit request mode
5
1
DIS
DIS
0
EN
EN
1
GC
General Call enable
2
1
DIS
DIS
0
EN
EN
1
GCSB
General call status bit clear
4
1
CLR
CLR
1
HGC
Hardware general Call enable
3
1
DIS
DIS
0
EN
EN
1
IENREPST
Repeated start interrupt enable
12
1
DIS
DIS
0
EN
EN
1
IENRX
Receive request interrupt enable
9
1
DIS
DIS
0
EN
EN
1
IENSTOP
Stop condition detected interrupt enable
8
1
DIS
DIS
0
EN
EN
1
IENTX
Transmit request interrupt enable
10
1
DIS
DIS
0
EN
EN
1
NACK
NACK next communication
7
1
DIS
DIS
0
EN
EN
1
RXDMA
Enable slave Rx DMA request
13
1
DIS
DIS
0
EN
EN
1
SLV
Slave Enable
0
1
DIS
DIS
0
EN
EN
1
STRETCH
Stretch SCL
6
1
DIS
DIS
0
EN
EN
1
TXDMA
Enable slave Tx DMA request
14
1
DIS
DIS
0
EN
EN
1
I2CSRX
Slave Receive Data Register
0x30
16
read-only
n
0x0
0x0
VALUE
Receive register
0
8
I2CSSTA
Slave I2C Status, Error and IRQ Register
0x2C
16
read-only
n
0x0
0x0
BUSY
Slave busy
6
1
CLR
CLR
0
SET
SET
1
GCID
General ID
8
2
CLR
CLR
0
SET
SET
1
GCINT
General call
7
1
CLR
CLR
0
SET
SET
1
IDMAT
Device ID matched
11
2
CLR
CLR
0
SET
SET
1
NOACK
Ack not generated by the slave
5
1
CLR
CLR
0
SET
SET
1
REPSTART
Repeated start and matching address
13
1
CLR
CLR
0
SET
SET
1
RXOF
Receive FIFO
4
1
CLR
CLR
0
SET
SET
1
RXREQ
Receive
3
1
CLR
CLR
0
SET
SET
1
START
Start and matching address
14
1
CLR
CLR
0
SET
SET
1
STOP
Stop after start and matching address
10
1
CLR
CLR
0
SET
SET
1
TXFSEREQ
Tx FIFO status or early request
0
1
CLR
CLR
0
SET
SET
1
TXREQ
Transmit
2
1
CLR
CLR
0
SET
SET
1
TXUR
Transmit FIFO underflow
1
1
CLR
CLR
0
SET
SET
1
I2CSTX
Slave Transmit Data Register
0x34
16
write-only
n
0x0
0x0
VALUE
Transmit register
0
8
ADI_INTERRUPT
Interrupts
INTERRUPT
0x0
0x0
0x18
registers
n
EINT0
1
EINT1
2
EINT2
3
EINT3
4
EINT4
5
EINT5
6
EINT6
7
EINT7
8
EI0CFG
External Interrupt configuration register 0
0x0
16
read-write
n
0x0
0x0
IRQ0EN
External Interrupt 0 Enable
3
1
DIS
DIS
0
EN
EN
1
IRQ0MDE
External Interrupt 0 Mode
0
3
RISE
RISE
0
FALL
FALL
1
RISEORFALL
RISEORFALL
2
HIGHLEVEL
HIGHLEVEL
3
LOWLEVEL
LOWLEVEL
4
IRQ1EN
External Interrupt 1 Enable
7
1
DIS
DIS
0
EN
EN
1
IRQ1MDE
External Interrupt 1 Mode
4
3
RISE
RISE
0
FALL
FALL
1
RISEORFALL
RISEORFALL
2
HIGHLEVEL
HIGHLEVEL
3
LOWLEVEL
LOWLEVEL
4
IRQ2EN
External Interrupt 2 Enable
11
1
DIS
DIS
0
EN
EN
1
IRQ2MDE
External Interrupt 2 Mode
8
3
RISE
RISE
0
FALL
FALL
1
RISEORFALL
RISEORFALL
2
HIGHLEVEL
HIGHLEVEL
3
LOWLEVEL
LOWLEVEL
4
IRQ3EN
External Interrupt 3 Enable
15
1
DIS
DIS
0
EN
EN
1
IRQ3MDE
External Interrupt 0 Mode
12
3
RISE
RISE
0
FALL
FALL
1
RISEORFALL
RISEORFALL
2
HIGHLEVEL
HIGHLEVEL
3
LOWLEVEL
LOWLEVEL
4
EI1CFG
External Interrupt configuration register 1
0x4
16
read-write
n
0x0
0x0
IRQ4EN
External Interrupt 4 Enable
3
1
DIS
DIS
0
EN
EN
1
IRQ4MDE
External Interrupt 4 Mode
0
3
RISE
RISE
0
FALL
FALL
1
RISEORFALL
RISEORFALL
2
HIGHLEVEL
HIGHLEVEL
3
LOWLEVEL
LOWLEVEL
4
IRQ5EN
External Interrupt 5 Enable
7
1
DIS
DIS
0
EN
EN
1
IRQ5MDE
External Interrupt 5 Mode
4
3
RISE
RISE
0
FALL
FALL
1
RISEORFALL
RISEORFALL
2
HIGHLEVEL
HIGHLEVEL
3
LOWLEVEL
LOWLEVEL
4
IRQ6EN
External Interrupt 6 Enable
11
1
DIS
DIS
0
EN
EN
1
IRQ6MDE
External Interrupt 6 Mode
8
3
RISE
RISE
0
FALL
FALL
1
RISEORFALL
RISEORFALL
2
HIGHLEVEL
HIGHLEVEL
3
LOWLEVEL
LOWLEVEL
4
IRQ7EN
External Interrupt 7 Enable
15
1
DIS
DIS
0
EN
EN
1
IRQ7MDE
External Interrupt 7 Mode
12
3
RISE
RISE
0
FALL
FALL
1
RISEORFALL
RISEORFALL
2
HIGHLEVEL
HIGHLEVEL
3
LOWLEVEL
LOWLEVEL
4
EICLR
External Interrupts Clear register
0x10
16
read-write
n
0x0
0x0
IRQ0
Clears External interrupt 0 internal flag
0
1
CLR
CLR
1
IRQ1
Clears External interrupt 1 internal flag
1
1
CLR
CLR
1
IRQ2
Clears External interrupt 2 internal flag
2
1
CLR
CLR
1
IRQ3
Clears External interrupt 3 internal flag
3
1
CLR
CLR
1
IRQ4
Clears External interrupt 4 internal flag
4
1
CLR
CLR
1
IRQ5
Clears External interrupt 5 internal flag
5
1
CLR
CLR
1
IRQ6
Clears External interrupt 6 internal flag
6
1
CLR
CLR
1
IRQ7
Clears External interrupt 7 internal flag
7
1
CLR
CLR
1
ADI_PWM
Pulse Width Modulation
PWM
0x0
0x0
0x40
registers
n
PWM_TRIP
35
PWM_PAIR0
36
PWM_PAIR1
37
PWM_PAIR2
38
PWM0COM0
Compare Register 0 for PWM0 and PWM1
0x10
16
read-write
n
0x0
0x0
PWM0COM1
Compare Register 1 for PWM0 and PWM1
0x14
16
read-write
n
0x0
0x0
PWM0COM2
Compare Register 2 for PWM0 and PWM1
0x18
16
read-write
n
0x0
0x0
PWM0LEN
Period Value register for PWM0 and PWM1
0x1C
16
read-write
n
0x0
0x0
PWM1COM0
Compare Register 0 for PWM2 and PWM3
0x20
16
read-write
n
0x0
0x0
PWM1COM1
Compare Register 1 for PWM2 and PWM3
0x24
16
read-write
n
0x0
0x0
PWM1COM2
Compare Register 2 for PWM2 and PWM3
0x28
16
read-write
n
0x0
0x0
PWM1LEN
Period Value register for PWM2 and PWM3
0x2C
16
read-write
n
0x0
0x0
PWM2COM0
Compare Register 0 for PWM4 and PWM5
0x30
16
read-write
n
0x0
0x0
PWM2COM1
Compare Register 1 for PWM4 and PWM5
0x34
16
read-write
n
0x0
0x0
PWM2COM2
Compare Register 2 for PWM4 and PWM5
0x38
16
read-write
n
0x0
0x0
PWM2LEN
Period Value register for PWM4 and PWM5
0x3C
16
read-write
n
0x0
0x0
PWMCLRI
PWM interrupt clear. Write to this register clears the latched PWM interrupt.
0x8
16
write-only
n
0x0
0x0
PWM0
Clear the latched PWM0 interrupt
0
1
DIS
DIS
0
EN
EN
1
PWM1
Clear the latched PWM1 interrupt
1
1
DIS
DIS
0
EN
EN
1
PWM2
Clear the latched PWM2 interrupt
2
1
DIS
DIS
0
EN
EN
1
TRIP
Clear the latched trip interrupt
4
1
DIS
DIS
0
EN
EN
1
PWMCON0
PWM Control register
0x0
16
read-write
n
0x0
0x0
DIR
Direction Control
2
1
DIS
DIS
0
EN
EN
1
ENA
enable PWM outputs
9
1
DIS
DIS
0
EN
EN
1
ENABLE
Enables all PWM outputs
0
1
DIS
DIS
0
EN
EN
1
HOFF
High Side Off
4
1
DIS
DIS
0
EN
EN
1
LCOMP
Load Compare Registers
3
1
DIS
DIS
0
EN
EN
1
MOD
Enables H-Bridge Mode
1
1
DIS
DIS
0
EN
EN
1
POINV
Invert all PWM outputs
5
1
DIS
DIS
0
EN
EN
1
PRE
PWM Clock Prescaler
6
3
PWM1INV
Inversion of PWM output
11
1
DIS
DIS
0
EN
EN
1
PWM3INV
Inversion of PWM output
12
1
DIS
DIS
0
EN
EN
1
PWM5INV
Inversion of PWM output
13
1
DIS
DIS
0
EN
EN
1
PWMIEN
Enables PWM interrupts
10
1
DIS
DIS
0
EN
EN
1
SYNC
PWM Synchronization
15
1
DIS
DIS
0
EN
EN
1
PWMCON1
Trip control register
0x4
8
read-write
n
0x0
0x0
CONVSTART
Enable adc conversion start from pwm
7
1
DIS
DIS
0
EN
EN
1
CONVSTARTDELAY
ADC conversion start delay configuration
0
4
TRIPEN
Enable PWM trip functionality
6
1
DIS
DIS
0
EN
EN
1
ADI_PWRCTL
Power Management Unit
PWRCTL
0x0
0x0
0x2C
registers
n
PWRKEY
Key protection for the PWRMOD register.
0x4
16
read-write
n
0x0
0x0
VALUE
Key value
0
16
KEY1
KEY1
18521
KEY2
KEY2
62075
PWRMOD
Power modes register
0x0
8
read-write
n
0x0
0x0
MOD
Power Mode
0
3
FULLACTIVE
FULLACTIVE
0
MCUHALT
MCUHALT
1
PERHALT
PERHALT
2
SYSHALT
SYSHALT
3
TOTALHALT
TOTALHALT
4
HIBERNATE
HIBERNATE
5
WICENACK
For Deepsleep mode only
3
1
DIS
DIS
0
EN
EN
1
ADI_RESET
Reset
RESET
0x0
0x0
0x4
registers
n
RSTCLR
Reset Status Clear
RSTSTA
0x0
8
write-only
n
0x0
0x0
EXTRST
External reset status bit
1
1
DIS
DIS
0
EN
EN
1
POR
Power-on reset status bit
0
1
DIS
DIS
0
EN
EN
1
SWRST
Software reset status bit
3
1
DIS
DIS
0
EN
EN
1
WDRST
Watchdog reset status bit
2
1
DIS
DIS
0
EN
EN
1
RSTSTA
Reset Status
0x0
8
read-only
n
0x0
0x0
EXTRST
External reset status bit
1
1
CLR
CLR
0
SET
SET
1
POR
Power-on reset status bit
0
1
CLR
CLR
0
SET
SET
1
SWRST
Software reset status bit
3
1
CLR
CLR
0
SET
SET
1
WDRST
Watchdog reset status bit
2
1
CLR
CLR
0
SET
SET
1
ADI_SPI0
Serial Peripheral Interface
SPI0
0x0
0x0
0x1C
registers
n
SPI0
18
SPI0CNT
8-bit received byte count register
0x18
16
read-only
n
0x0
0x0
VALUE
Count
0
8
SPI0CON
16-bit configuration register
0x10
16
read-write
n
0x0
0x0
CON
Continuous transfer enable
11
1
DIS
DIS
0
EN
EN
1
CPHA
Clock phase mode
2
1
SAMPLELEADING
SAMPLELEADING
0
SAMPLETRAILING
SAMPLETRAILING
1
CPOL
Clock polarity mode
3
1
LOW
LOW
0
HIGH
HIGH
1
ENABLE
SPI Enable bit
0
1
DIS
DIS
0
EN
EN
1
LOOPBACK
Loopback enable bit
10
1
DIS
DIS
0
EN
EN
1
LSB
LSB First Transfer enable
5
1
DIS
DIS
0
EN
EN
1
MASEN
Master enable
1
1
DIS
DIS
0
EN
EN
1
MOD
SPI IRQ Mode bits
14
2
TX1RX1
None
0
TX2RX2
TX2RX2
1
TX3RX3
TX3RX3
2
TX4RX4
TX4RX4
3
RFLUSH
RX FIFO Flush Enable bit
12
1
DIS
DIS
0
EN
EN
1
RXOF
RX Oveflow Overwrite enable
8
1
DIS
DIS
0
EN
EN
1
SOEN
Slave MISO output enable bit
9
1
DIS
DIS
0
EN
EN
1
TFLUSH
TX FIFO Flush Enable bit
13
1
DIS
DIS
0
EN
EN
1
TIM
Transfer and interrupt mode
6
1
RXRD
- Cleared by user to initiate transfer with a read of the SPIRX register
0
TXWR
- Set by user to initiate transfer with a write to the SPITX register.
1
WOM
Wired OR enable
4
1
DIS
DIS
0
EN
EN
1
ZEN
Transmit zeros when empty
7
1
DIS
DIS
0
EN
EN
1
SPI0DIV
SPI Clock Divider Registers
0xC
16
read-write
n
0x0
0x0
BCRST
Bit counter reset
7
1
DIS
DIS
0
EN
EN
1
DIV
Factor used to divide UCLK to generate the serial clock
0
6
SPI0DMA
DMA enable register
0x14
16
read-write
n
0x0
0x0
ENABLE
Enable DMA for data transfer
0
1
DIS
DIS
0
EN
EN
1
IENRXDMA
Enable receive DMA request
2
1
DIS
DIS
0
EN
EN
1
IENTXDMA
Enable transmit DMA request
1
1
DIS
DIS
0
EN
EN
1
SPI0RX
8-bit Receive register.
0x4
8
read-only
n
0x0
0x0
VALUE
Received data
0
8
SPI0STA
Status Register
0x0
16
read-only
n
0x0
0x0
CSERR
Detected an abrupt CS deassertion
12
1
CLR
CLR
0
SET
SET
1
IRQ
Interrupt status bit
0
1
CLR
CLR
0
SET
SET
1
RX
Set when a receive interrupt occurs
6
1
CLR
CLR
0
SET
SET
1
RXFSTA
Receive FIFO Status
8
3
EMPTY
EMPTY
0
ONEBYTE
ONEBYTE
1
TWOBYTES
TWOBYTES
2
THREEBYTES
THREEBYTES
3
FOURBYTES
FOURBYTES
4
RXOF
Receive FIFO overflow
7
1
CLR
CLR
0
SET
SET
1
RXS
Set when there are more bytes in the RX FIFO than the TIM bit says
11
1
CLR
CLR
0
SET
SET
1
TX
Set when a transmit interrupt occurs
5
1
CLR
CLR
0
SET
SET
1
TXFSTA
transmit FIFO Status
1
3
EMPTY
EMPTY
0
ONEBYTE
ONEBYTE
1
TWOBYTES
TWOBYTES
2
THREEBYTES
THREEBYTES
3
FOURBYTES
FOURBYTES
4
TXUR
Transmit FIFO underflow
4
1
CLR
CLR
0
SET
SET
1
SPI0TX
8-bit Transmit register
0x8
8
write-only
n
0x0
0x0
VALUE
Data to transmit
0
8
ADI_SPI1
Serial Peripheral Interface
SPI1
0x0
0x0
0x1C
registers
n
SPI1
19
SPI1CNT
8-bit received byte count register
0x18
16
read-only
n
0x0
0x0
VALUE
Count
0
8
SPI1CON
16-bit configuration register
0x10
16
read-write
n
0x0
0x0
CON
Continuous transfer enable
11
1
DIS
DIS
0
EN
EN
1
CPHA
Clock phase mode
2
1
SAMPLELEADING
SAMPLELEADING
0
SAMPLETRAILING
SAMPLETRAILING
1
CPOL
Clock polarity mode
3
1
LOW
LOW
0
HIGH
HIGH
1
ENABLE
SPI Enable bit
0
1
DIS
DIS
0
EN
EN
1
LOOPBACK
Loopback enable bit
10
1
DIS
DIS
0
EN
EN
1
LSB
LSB First Transfer enable
5
1
DIS
DIS
0
EN
EN
1
MASEN
Master enable
1
1
DIS
DIS
0
EN
EN
1
MOD
SPI IRQ Mode bits
14
2
TX1RX1
TX1RX1
0
TX2RX2
TX2RX2
1
TX3RX3
TX3RX3
2
TX4RX4
TX4RX4
3
RFLUSH
RX FIFO Flush Enable bit
12
1
DIS
DIS
0
EN
EN
1
RXOF
RX Oveflow Overwrite enable
8
1
DIS
DIS
0
EN
EN
1
SOEN
Slave MISO output enable bit
9
1
DIS
DIS
0
EN
EN
1
TFLUSH
TX FIFO Flush Enable bit
13
1
DIS
DIS
0
EN
EN
1
TIM
Transfer and interrupt mode
6
1
RXRD
- Cleared by user to initiate transfer with a read of the SPIRX register
0
TXWR
- Set by user to initiate transfer with a write to the SPITX register.
1
WOM
Wired OR enable
4
1
DIS
DIS
0
EN
EN
1
ZEN
Transmit zeros when empty
7
1
DIS
DIS
0
EN
EN
1
SPI1DIV
SPI Clock Divider Registers
0xC
16
read-write
n
0x0
0x0
BCRST
Bit counter reset
7
1
DIS
DIS
0
EN
EN
1
DIV
Factor used to divide UCLK to generate the serial clock
0
6
SPI1DMA
DMA enable register
0x14
16
read-write
n
0x0
0x0
ENABLE
Enable DMA for data transfer
0
1
DIS
DIS
0
EN
EN
1
IENRXDMA
Enable receive DMA request
2
1
DIS
DIS
0
EN
EN
1
IENTXDMA
Enable transmit DMA request
1
1
DIS
DIS
0
EN
EN
1
SPI1RX
8-bit Receive register.
0x4
8
read-only
n
0x0
0x0
VALUE
Received data
0
8
SPI1STA
Status Register
0x0
16
read-only
n
0x0
0x0
CSERR
Detected an abrupt CS deassertion
12
1
CLR
CLR
0
SET
SET
1
IRQ
Interrupt status bit
0
1
CLR
CLR
0
SET
SET
1
RX
Set when a receive interrupt occurs
6
1
CLR
CLR
0
SET
SET
1
RXFSTA
Receive FIFO Status
8
3
EMPTY
EMPTY
0
ONEBYTE
ONEBYTE
1
TWOBYTES
TWOBYTES
2
THREEBYTES
THREEBYTES
3
FOURBYTES
FOURBYTES
4
RXOF
Receive FIFO overflow
7
1
CLR
CLR
0
SET
SET
1
RXS
Set when there are more bytes in the RX FIFO than the TIM bit says
11
1
CLR
CLR
0
SET
SET
1
TX
Set when a transmit interrupt occurs
5
1
CLR
CLR
0
SET
SET
1
TXFSTA
transmit FIFO Status
1
3
EMPTY
EMPTY
0
ONEBYTE
ONEBYTE
1
TWOBYTES
TWOBYTES
2
THREEBYTES
THREEBYTES
3
FOURBYTES
FOURBYTES
4
TXUR
Transmit FIFO underflow
4
1
CLR
CLR
0
SET
SET
1
SPI1TX
8-bit Transmit register
0x8
8
write-only
n
0x0
0x0
VALUE
Data to transmit
0
8
ADI_T0
Timer 0
T0
0x0
0x0
0x20
registers
n
TIMER0
11
T0CAP
Capture Register
0x10
16
read-only
n
0x0
0x0
VALUE
Capture value
0
16
T0CLRI
Clear interrupt register
0xC
16
read-write
n
0x0
0x0
CAP
Clear captured event interrupt
1
1
CLR
CLR
1
TMOUT
Clear timeout interrupt
0
1
CLR
CLR
1
T0CON
Control Register
0x8
16
read-write
n
0x0
0x0
CLK
Clock Select
5
2
UCLK
- System Clock
0
PCLK
- Peripheral clock
1
LFOSC
- Internal 32 kHz Oscillator
2
LFXTAL
- External 32 kHz crystal
3
ENABLE
Enable
4
1
DIS
DIS
0
EN
EN
1
EVENT
Event Select, selects 1 of the available events.
8
4
T2
- Wakeup Timer
0
EXT0
- External interrupt 0
1
T1
- Timer1
10
ADC0
- ADC0
11
ADC1
- ADC1
12
STEP
- STEP
13
DMADONE
DMADONE
14
FEE
- Flash controller
15
EXT1
- External interrupt 1
2
EXT2
- External interrupt 2
3
EXT3
- External interrupt 3
4
EXT4
- External interrupt 4
5
EXT5
- External interrupt 5
6
EXT6
- External interrupt 6
7
EXT7
- External interrupt 7
8
T3
- Watchdog timer
9
EVENTEN
Enable time capture of an event
12
1
DIS
DIS
0
EN
EN
1
MOD
Mode
3
1
FREERUN
FREERUN
0
PERIODIC
PERIODIC
1
PRE
Prescaler
0
2
DIV1
DIV1
0
DIV16
DIV16
1
DIV256
DIV256
2
DIV32768
- If the selected clock source is UCLK then this setting results in a prescaler of 4.
3
RLD
Timer reload on write to clear register
7
1
DIS
DIS
0
EN
EN
1
UP
Count-up
2
1
DIS
DIS
0
EN
EN
1
T0LD
16-bit load value
0x0
16
read-write
n
0x0
0x0
VALUE
Load value
0
16
T0STA
Status Register
0x1C
16
read-only
n
0x0
0x0
CAP
Capture event pending
1
1
CLR
CLR
0
SET
SET
1
CLRI
Value updated in the timer clock domain
7
1
CLR
CLR
0
SET
SET
1
CON
Ready to receive commands
6
1
CLR
CLR
0
SET
SET
1
TMOUT
Time out event occurred
0
1
CLR
CLR
0
SET
SET
1
T0VAL
16-bit timer value, read only.
0x4
16
read-only
n
0x0
0x0
VALUE
Current value
0
16
ADI_T1
Timer 1
T1
0x0
0x0
0x20
registers
n
TIMER1
12
T1CAP
Capture Register
0x10
16
read-only
n
0x0
0x0
VALUE
Capture value
0
16
T1CLRI
Clear interrupt register
0xC
16
read-write
n
0x0
0x0
CAP
Clear captured event interrupt
1
1
CLR
CLR
1
TMOUT
Clear timeout interrupt
0
1
CLR
CLR
1
T1CON
Control Register
0x8
16
read-write
n
0x0
0x0
CLK
Clock Select
5
2
UCLK
- System Clock
0
PCLK
- Peripheral clock
1
LFOSC
- Internal 32 kHz Oscillator
2
LFXTAL
- External 32 kHz crystal
3
ENABLE
Enable
4
1
DIS
DIS
0
EN
EN
1
EVENT
Event Select, selects 1 of the available events.
8
4
COM
COM
0
T0
- Timer0
1
EXT3
EXT3
10
PWMTRIP
PWMTRIP
11
PWM0
PWM0
12
PWM1
PWM1
13
PWM2
PWM2
14
ADC0
ADC0
15
SPI0
SPI0
2
SPI1
SPI1
3
I2CS
I2CS
4
I2CM
I2CM
5
DMAERR
DMAERR
6
DMADONE
DMADONE
7
EXT1
EXT1
8
EXT2
EXT2
9
EVENTEN
Enable time capture of an event
12
1
DIS
DIS
0
EN
EN
1
MOD
Mode
3
1
FREERUN
FREERUN
0
PERIODIC
PERIODIC
1
PRE
Prescaler
0
2
DIV1
DIV1
0
DIV16
DIV16
1
DIV256
DIV256
2
DIV32768
- If the selected clock source is UCLK then this setting results in a prescaler of 4.
3
RLD
Timer reload on write to clear register
7
1
DIS
DIS
0
EN
EN
1
UP
Count-up
2
1
DIS
DIS
0
EN
EN
1
T1LD
16-bit load value
0x0
16
read-write
n
0x0
0x0
VALUE
Load value
0
16
T1STA
Status Register
0x1C
16
read-only
n
0x0
0x0
CAP
Capture event pending
1
1
CLR
CLR
0
SET
SET
1
CLRI
Value updated in the timer clock domain
7
1
CLR
CLR
0
SET
SET
1
CON
Ready to receive commands
6
1
CLR
CLR
0
SET
SET
1
TMOUT
Time out event occurred
0
1
CLR
CLR
0
SET
SET
1
T1VAL
16-bit timer value, read only.
0x4
16
read-only
n
0x0
0x0
VALUE
Current value
0
16
ADI_UART0
UART0
UART
0x0
0x0
0x30
registers
n
COMCON
UART control register
0x30
8
read-write
n
0x0
0x0
DISABLE
Uart Disable
0
1
DIS
DIS
0
EN
EN
1
COMDIV
Baud rate Divisor register
0x28
16
read-write
n
0x0
0x0
VALUE
Sets the baudrate
0
16
COMFBR
Fractional baud rate divider register.
0x24
16
read-write
n
0x0
0x0
DIVM
Fractional M Divide bits
11
2
DIVN
Fractional N Divide bits
0
11
ENABLE
Enable
15
1
DIS
DIS
0
EN
EN
1
COMIEN
Interrupt Enable register
0x4
8
read-write
n
0x0
0x0
EDMAR
Enable DMA requests in transmit mode
5
1
DIS
DIS
0
EN
EN
1
EDMAT
Enable DMA requests in receive mode
4
1
DIS
DIS
0
EN
EN
1
EDSSI
Enable Modem Status interrupt
3
1
DIS
DIS
0
EN
EN
1
ELSI
Enable Rx status interrupt
2
1
DIS
DIS
0
EN
EN
1
ERBFI
Enable receive buffer full interrupt
0
1
DIS
DIS
0
EN
EN
1
ETBEI
Enable transmit buffer empty interrupt
1
1
DIS
DIS
0
EN
EN
1
COMIIR
Interrupt Identification register
0x8
8
read-only
n
0x0
0x0
NINT
Interrupt flag.
0
1
CLR
CLR
0
SET
SET
1
STA
Status bits.
1
2
MODEMSTATUS
- Modem status interrupt.
0
TXBUFEMPTY
- Transmit buffer empty interrupt.
1
RXBUFFULL
- Receive buffer full interrupt. Read RBR register to clear.
2
RXLINESTATUS
- Receive line status interrupt. Read LSR register to clear.
3
COMLCR
Line Control register
0xC
8
read-write
n
0x0
0x0
BRK
Set Break.
6
1
DIS
DIS
0
EN
EN
1
EPS
Even Parity Select Bit.
4
1
DIS
DIS
0
EN
EN
1
PEN
Parity Enable Bit.
3
1
DIS
DIS
0
EN
EN
1
SP
Stick Parity.
5
1
DIS
DIS
0
EN
EN
1
STOP
Stop Bit.
2
1
DIS
DIS
0
EN
EN
1
WLS
Word Length Select bits
0
2
5BITS
5BITS
0
6BITS
6BITS
1
7BITS
7BITS
2
8BITS
8BITS
3
COMLSR
Line Status register
0x14
8
read-only
n
0x0
0x0
BI
Break Indicator.
4
1
CLR
CLR
0
SET
SET
1
DR
Data Ready.
0
1
CLR
CLR
0
SET
SET
1
FE
Framing Error.
3
1
CLR
CLR
0
SET
SET
1
OE
Overrun Error.
1
1
CLR
CLR
0
SET
SET
1
PE
Parity Error.
2
1
CLR
CLR
0
SET
SET
1
TEMT
COMTX and Shift Register Empty Status Bit.
6
1
CLR
CLR
0
SET
SET
1
THRE
COMTX Empty Status Bit.
5
1
CLR
CLR
0
SET
SET
1
COMMCR
Module Control register
0x10
8
read-write
n
0x0
0x0
DTR
Data Terminal Ready.
0
1
DIS
DIS
0
EN
EN
1
LOOPBACK
Loop Back.
4
1
DIS
DIS
0
EN
EN
1
OUT1
Parity Enable Bit.
3
1
DIS
DIS
0
EN
EN
1
OUT2
Stop Bit.
2
1
DIS
DIS
0
EN
EN
1
RTS
Request To Send.
1
1
DIS
DIS
0
EN
EN
1
COMMSR
Modem Status register
0x18
8
read-only
n
0x0
0x0
CTS
Clear To Send.
4
1
DIS
DIS
0
EN
EN
1
DCD
Data Carrier Detect.
7
1
DIS
DIS
0
EN
EN
1
DCTS
Delta CTS.
0
1
DIS
DIS
0
EN
EN
1
DDCD
Delta DCD.
3
1
DIS
DIS
0
EN
EN
1
DDSR
Delta DSR.
1
1
DIS
DIS
0
EN
EN
1
DSR
Data Set Ready.
5
1
DIS
DIS
0
EN
EN
1
RI
Ring Indicator.
6
1
DIS
DIS
0
EN
EN
1
TERI
Trailing Edge RI.
2
1
DIS
DIS
0
EN
EN
1
COMRX
Receive Buffer register
COMTX
0x0
8
read-only
n
0x0
0x0
VALUE
Value
0
8
COMTX
Transmit Holding register
0x0
8
write-only
n
0x0
0x0
VALUE
Value
0
8
ADI_UART1
UART1
UART
0x0
0x0
0x30
registers
n
COMCON
UART control register
0x30
8
read-write
n
0x0
0x0
DISABLE
Uart Disable
0
1
DIS
DIS
0
EN
EN
1
COMDIV
Baud rate Divisor register
0x28
16
read-write
n
0x0
0x0
VALUE
Sets the baudrate
0
16
COMFBR
Fractional baud rate divider register.
0x24
16
read-write
n
0x0
0x0
DIVM
Fractional M Divide bits
11
2
DIVN
Fractional N Divide bits
0
11
ENABLE
Enable
15
1
DIS
DIS
0
EN
EN
1
COMIEN
Interrupt Enable register
0x4
8
read-write
n
0x0
0x0
EDMAR
Enable DMA requests in transmit mode
5
1
DIS
DIS
0
EN
EN
1
EDMAT
Enable DMA requests in receive mode
4
1
DIS
DIS
0
EN
EN
1
EDSSI
Enable Modem Status interrupt
3
1
DIS
DIS
0
EN
EN
1
ELSI
Enable Rx status interrupt
2
1
DIS
DIS
0
EN
EN
1
ERBFI
Enable receive buffer full interrupt
0
1
DIS
DIS
0
EN
EN
1
ETBEI
Enable transmit buffer empty interrupt
1
1
DIS
DIS
0
EN
EN
1
COMIIR
Interrupt Identification register
0x8
8
read-only
n
0x0
0x0
NINT
Interrupt flag.
0
1
CLR
CLR
0
SET
SET
1
STA
Status bits.
1
2
MODEMSTATUS
- Modem status interrupt.
0
TXBUFEMPTY
- Transmit buffer empty interrupt.
1
RXBUFFULL
- Receive buffer full interrupt. Read RBR register to clear.
2
RXLINESTATUS
- Receive line status interrupt. Read LSR register to clear.
3
COMLCR
Line Control register
0xC
8
read-write
n
0x0
0x0
BRK
Set Break.
6
1
DIS
DIS
0
EN
EN
1
EPS
Even Parity Select Bit.
4
1
DIS
DIS
0
EN
EN
1
PEN
Parity Enable Bit.
3
1
DIS
DIS
0
EN
EN
1
SP
Stick Parity.
5
1
DIS
DIS
0
EN
EN
1
STOP
Stop Bit.
2
1
DIS
DIS
0
EN
EN
1
WLS
Word Length Select bits
0
2
5BITS
5BITS
0
6BITS
6BITS
1
7BITS
7BITS
2
8BITS
8BITS
3
COMLSR
Line Status register
0x14
8
read-only
n
0x0
0x0
BI
Break Indicator.
4
1
CLR
CLR
0
SET
SET
1
DR
Data Ready.
0
1
CLR
CLR
0
SET
SET
1
FE
Framing Error.
3
1
CLR
CLR
0
SET
SET
1
OE
Overrun Error.
1
1
CLR
CLR
0
SET
SET
1
PE
Parity Error.
2
1
CLR
CLR
0
SET
SET
1
TEMT
COMTX and Shift Register Empty Status Bit.
6
1
CLR
CLR
0
SET
SET
1
THRE
COMTX Empty Status Bit.
5
1
CLR
CLR
0
SET
SET
1
COMMCR
Module Control register
0x10
8
read-write
n
0x0
0x0
DTR
Data Terminal Ready.
0
1
DIS
DIS
0
EN
EN
1
LOOPBACK
Loop Back.
4
1
DIS
DIS
0
EN
EN
1
OUT1
Parity Enable Bit.
3
1
DIS
DIS
0
EN
EN
1
OUT2
Stop Bit.
2
1
DIS
DIS
0
EN
EN
1
RTS
Request To Send.
1
1
DIS
DIS
0
EN
EN
1
COMMSR
Modem Status register
0x18
8
read-only
n
0x0
0x0
CTS
Clear To Send.
4
1
DIS
DIS
0
EN
EN
1
DCD
Data Carrier Detect.
7
1
DIS
DIS
0
EN
EN
1
DCTS
Delta CTS.
0
1
DIS
DIS
0
EN
EN
1
DDCD
Delta DCD.
3
1
DIS
DIS
0
EN
EN
1
DDSR
Delta DSR.
1
1
DIS
DIS
0
EN
EN
1
DSR
Data Set Ready.
5
1
DIS
DIS
0
EN
EN
1
RI
Ring Indicator.
6
1
DIS
DIS
0
EN
EN
1
TERI
Trailing Edge RI.
2
1
DIS
DIS
0
EN
EN
1
COMRX
Receive Buffer register
COMTX
0x0
8
read-only
n
0x0
0x0
VALUE
Value
0
8
COMTX
Transmit Holding register
0x0
8
write-only
n
0x0
0x0
VALUE
Value
0
8
ADI_UART2
UART2
UART
0x0
0x0
0x30
registers
n
COMCON
UART control register
0x30
8
read-write
n
0x0
0x0
DISABLE
Uart Disable
0
1
DIS
DIS
0
EN
EN
1
COMDIV
Baud rate Divisor register
0x28
16
read-write
n
0x0
0x0
VALUE
Sets the baudrate
0
16
COMFBR
Fractional baud rate divider register.
0x24
16
read-write
n
0x0
0x0
DIVM
Fractional M Divide bits
11
2
DIVN
Fractional N Divide bits
0
11
ENABLE
Enable
15
1
DIS
DIS
0
EN
EN
1
COMIEN
Interrupt Enable register
0x4
8
read-write
n
0x0
0x0
EDMAR
Enable DMA requests in transmit mode
5
1
DIS
DIS
0
EN
EN
1
EDMAT
Enable DMA requests in receive mode
4
1
DIS
DIS
0
EN
EN
1
EDSSI
Enable Modem Status interrupt
3
1
DIS
DIS
0
EN
EN
1
ELSI
Enable Rx status interrupt
2
1
DIS
DIS
0
EN
EN
1
ERBFI
Enable receive buffer full interrupt
0
1
DIS
DIS
0
EN
EN
1
ETBEI
Enable transmit buffer empty interrupt
1
1
DIS
DIS
0
EN
EN
1
COMIIR
Interrupt Identification register
0x8
8
read-only
n
0x0
0x0
NINT
Interrupt flag.
0
1
CLR
CLR
0
SET
SET
1
STA
Status bits.
1
2
MODEMSTATUS
- Modem status interrupt.
0
TXBUFEMPTY
- Transmit buffer empty interrupt.
1
RXBUFFULL
- Receive buffer full interrupt. Read RBR register to clear.
2
RXLINESTATUS
- Receive line status interrupt. Read LSR register to clear.
3
COMLCR
Line Control register
0xC
8
read-write
n
0x0
0x0
BRK
Set Break.
6
1
DIS
DIS
0
EN
EN
1
EPS
Even Parity Select Bit.
4
1
DIS
DIS
0
EN
EN
1
PEN
Parity Enable Bit.
3
1
DIS
DIS
0
EN
EN
1
SP
Stick Parity.
5
1
DIS
DIS
0
EN
EN
1
STOP
Stop Bit.
2
1
DIS
DIS
0
EN
EN
1
WLS
Word Length Select bits
0
2
5BITS
5BITS
0
6BITS
6BITS
1
7BITS
7BITS
2
8BITS
8BITS
3
COMLSR
Line Status register
0x14
8
read-only
n
0x0
0x0
BI
Break Indicator.
4
1
CLR
CLR
0
SET
SET
1
DR
Data Ready.
0
1
CLR
CLR
0
SET
SET
1
FE
Framing Error.
3
1
CLR
CLR
0
SET
SET
1
OE
Overrun Error.
1
1
CLR
CLR
0
SET
SET
1
PE
Parity Error.
2
1
CLR
CLR
0
SET
SET
1
TEMT
COMTX and Shift Register Empty Status Bit.
6
1
CLR
CLR
0
SET
SET
1
THRE
COMTX Empty Status Bit.
5
1
CLR
CLR
0
SET
SET
1
COMMCR
Module Control register
0x10
8
read-write
n
0x0
0x0
DTR
Data Terminal Ready.
0
1
DIS
DIS
0
EN
EN
1
LOOPBACK
Loop Back.
4
1
DIS
DIS
0
EN
EN
1
OUT1
Parity Enable Bit.
3
1
DIS
DIS
0
EN
EN
1
OUT2
Stop Bit.
2
1
DIS
DIS
0
EN
EN
1
RTS
Request To Send.
1
1
DIS
DIS
0
EN
EN
1
COMMSR
Modem Status register
0x18
8
read-only
n
0x0
0x0
CTS
Clear To Send.
4
1
DIS
DIS
0
EN
EN
1
DCD
Data Carrier Detect.
7
1
DIS
DIS
0
EN
EN
1
DCTS
Delta CTS.
0
1
DIS
DIS
0
EN
EN
1
DDCD
Delta DCD.
3
1
DIS
DIS
0
EN
EN
1
DDSR
Delta DSR.
1
1
DIS
DIS
0
EN
EN
1
DSR
Data Set Ready.
5
1
DIS
DIS
0
EN
EN
1
RI
Ring Indicator.
6
1
DIS
DIS
0
EN
EN
1
TERI
Trailing Edge RI.
2
1
DIS
DIS
0
EN
EN
1
COMRX
Receive Buffer register
COMTX
0x0
8
read-only
n
0x0
0x0
VALUE
Value
0
8
COMTX
Transmit Holding register
0x0
8
write-only
n
0x0
0x0
VALUE
Value
0
8
ADI_WDT
Watchdog Timer
WDT
0x0
0x0
0x1C
registers
n
T3CLRI
Clear interrupt, write only.
0xC
16
write-only
n
0x0
0x0
VALUE
Clear Watchdog
0
16
CLR
CLR
52428
T3CON
Control Register
0x8
16
read-write
n
0x0
0x0
ENABLE
Enable
5
1
DIS
DIS
0
EN
EN
1
IRQ
Timer Interrupt ,
1
1
DIS
DIS
0
EN
EN
1
MOD
Mode
6
1
FREERUN
FREERUN
0
PERIODIC
PERIODIC
1
PD
Power down clear
0
1
DIS
DIS
0
EN
EN
1
PRE
Prescaler
2
2
DIV1
DIV1
0
DIV16
DIV16
1
DIV256
DIV256
2
DIV4096
DIV4096
3
T3LD
Load value.
0x0
16
read-write
n
0x0
0x0
VALUE
Current Value
0
16
T3STA
Status register, read only.
0x18
16
read-only
n
0x0
0x0
CLRI
T3CLRI write sync in progress
1
1
CLR
CLR
0
SET
SET
1
CON
T3CON write sync in progress
3
1
CLR
CLR
0
SET
SET
1
IRQ
Interrupt Pending
0
1
CLR
CLR
0
SET
SET
1
LD
T3LD write sync in progress
2
1
CLR
CLR
0
SET
SET
1
LOCK
Lock status bit
4
1
CLR
CLR
0
SET
SET
1
T3VAL
Current count value, read only.
0x4
16
read-only
n
0x0
0x0
VALUE
Current Value
0
16
ADI_WUT
WakeUp Timer
WUT
0x0
0x0
0x44
registers
n
T2CLRI
Clear interrupts. Write only.
0x30
16
write-only
n
0x0
0x0
ROLL
Clear interrupt on Rollover
4
1
CLR
CLR
1
WUFA
Clear interrupt on WUFA
0
1
CLR
CLR
1
WUFB
Clear interrupt on WUFB
1
1
CLR
CLR
1
WUFC
Clear interrupt on WUFC
2
1
CLR
CLR
1
WUFD
Clear interrupt on WUFD
3
1
CLR
CLR
1
T2CON
Control Register
0x8
16
read-write
n
0x0
0x0
CLK
Clock
9
2
PCLK
PCLK
0
LFXTAL
LFXTAL
1
LFOSC
LFOSC
2
EXTCLK
EXTCLK
3
ENABLE
Enable
7
1
DIS
DIS
0
EN
EN
1
FREEZE
Freeze
3
1
DIS
DIS
0
EN
EN
1
MOD
Mode
6
1
PERIODIC
PERIODIC
0
FREERUN
FREERUN
1
PRE
Prescaler
0
2
DIV1
DIV1
0
DIV16
DIV16
1
DIV256
DIV256
2
DIV32768
DIV32768
3
STOPINC
Stop wake up field A being updated
11
1
DIS
DIS
0
EN
EN
1
WUEN
WUEN
8
1
DIS
DIS
0
EN
EN
1
T2IEN
Interrupt enable
0x28
16
read-write
n
0x0
0x0
ROLL
Enable interrupt on Rollover
4
1
DIS
DIS
0
EN
EN
1
WUFA
Enable interrupt on WUFA
0
1
DIS
DIS
0
EN
EN
1
WUFB
Enable interrupt on WUFB
1
1
DIS
DIS
0
EN
EN
1
WUFC
Enable interrupt on WUFC
2
1
DIS
DIS
0
EN
EN
1
WUFD
Enable interrupt on WUFD
3
1
DIS
DIS
0
EN
EN
1
T2INC
12-bit register. Wake up field A
0xC
16
read-write
n
0x0
0x0
VALUE
12 bit value
0
12
T2STA
Status
0x2C
16
read-only
n
0x0
0x0
CON
Sync
8
1
CLR
CLR
0
SET
SET
1
FREEZE
Timer Value Freeze
7
1
CLR
CLR
0
SET
SET
1
ROLL
Rollover Interrupt
4
1
CLR
CLR
0
SET
SET
1
WUFA
WUFA Interrupt
0
1
CLR
CLR
0
SET
SET
1
WUFB
WUFB Interrupt
1
1
CLR
CLR
0
SET
SET
1
WUFC
WUFC Interrupt
2
1
CLR
CLR
0
SET
SET
1
WUFD
WUFD Interrupt
3
1
CLR
CLR
0
SET
SET
1
T2VAL0
Current count value LSB
0x0
16
read-only
n
0x0
0x0
VALUE
Current Value
0
16
T2VAL1
Current count value MSB
0x4
16
read-only
n
0x0
0x0
VALUE
Current Value
0
16
T2WUFA0
Wake up field A LSB.
0x3C
16
read-write
n
0x0
0x0
VALUE
Current Value
0
16
T2WUFA1
Wake up field A MSB.
0x40
16
read-write
n
0x0
0x0
VALUE
Current Value
0
16
T2WUFB0
Wake up field B LSB
0x10
16
read-write
n
0x0
0x0
VALUE
Current Value
0
16
T2WUFB1
Wake up field B MSB
0x14
16
read-write
n
0x0
0x0
VALUE
Current Value
0
16
T2WUFC0
Wake up field C LSB
0x18
16
read-write
n
0x0
0x0
VALUE
Current Value
0
16
T2WUFC1
Wake up field C MSB
0x1C
16
read-write
n
0x0
0x0
VALUE
Current Value
0
16
T2WUFD0
Wake up field D LSB
0x20
16
read-write
n
0x0
0x0
VALUE
Current Value
0
16
T2WUFD1
Wake up field D MSB
0x24
16
read-write
n
0x0
0x0
VALUE
Current Value
0
16
NVIC
Nested Vectored Interrupt Controller
NVIC
0x0
0x0
0xF04
registers
n
AIRCR
Application Interrupt and Reset Control Register
0xD0C
32
read-write
n
0x0
0x0
ENDIANESS
This bit is static or configured by a hardware input on reset
15
1
DIS
DIS
0
EN
EN
1
PRIGROUP
Priority grouping position
8
3
SYSRESETREQ
System Reset Request
2
1
DIS
DIS
0
EN
EN
1
VECTCLRACTIVE
Clears all active state information for fixed and configurable exceptions
1
1
DIS
DIS
0
EN
EN
1
VECTKEYSTAT
Reads as 0xFA05
16
16
VECTRESET
Local system reset
0
1
DIS
DIS
0
EN
EN
1
BFAR
Bus Fault Address
0xD38
32
read-write
n
0x0
0x0
ADDRESS
Updated on precise data access faults
0
32
CCR
Configuration Control
0xD14
32
read-write
n
0x0
0x0
BFHFNMIGN
TBD
8
1
DIS
DIS
0
EN
EN
1
DIV0TRP
TBD
4
1
DIS
DIS
0
EN
EN
1
NONBASETHRDENA
TBD
0
1
DIS
DIS
0
EN
EN
1
STKALIGN
TBD
9
1
DIS
DIS
0
EN
EN
1
UNALIGNTRP
TBD
3
1
DIS
DIS
0
EN
EN
1
USERSETMPEND
TBD
1
1
DIS
DIS
0
EN
EN
1
CFSR
Configurable Fault Status
0xD28
32
read-write
n
0x0
0x0
BFARVALID
This bit is set if the BFAR register has valid contents
15
1
DIS
DIS
0
EN
EN
1
DACCVIOL
Data access violation. The MMAR is set to the data address which the load store tried to access.
1
1
DIS
DIS
0
EN
EN
1
DIVBYZERO
Divide by zero error
25
1
DIS
DIS
0
EN
EN
1
IACCVIOL
violation on an instruction fetch.
0
1
DIS
DIS
0
EN
EN
1
IBUSERR
This bit indicates a bus fault on an instruction prefetch
8
1
DIS
DIS
0
EN
EN
1
IMPRECISERR
Imprecise data access error
10
1
DIS
DIS
0
EN
EN
1
INVPC
Integrity check error on EXC_RETURN
18
1
DIS
DIS
0
EN
EN
1
INVSTATE
Invalid EPSR.T bit or illegal EPSR.IT bits for executing
17
1
DIS
DIS
0
EN
EN
1
MMARVALID
This bit is set if the MMAR register has valid contents.
7
1
DIS
DIS
0
EN
EN
1
MSTKERR
A derived MemManage fault has occurred on exception entry
4
1
DIS
DIS
0
EN
EN
1
MUNSTKERR
A derived MemManage fault has occurred on exception return
3
1
DIS
DIS
0
EN
EN
1
NOCP
Coprocessor access error
19
1
DIS
DIS
0
EN
EN
1
PRECISERR
Precise data access error. The BFAR is written with the faulting address
9
1
DIS
DIS
0
EN
EN
1
STKERR
This bit indicates a derived bus fault has occurred on exception entry
12
1
DIS
DIS
0
EN
EN
1
UNALIGNED
Unaligned access error
24
1
DIS
DIS
0
EN
EN
1
UNDEFINSTR
Undefined instruction executed
16
1
DIS
DIS
0
EN
EN
1
UNSTKERR
This bit indicates a derived bus fault has occurred on exception return
11
1
DIS
DIS
0
EN
EN
1
CPUID
CPUID Base
0xD00
32
read-only
n
0x0
0x0
IMPLEMENTER
Indicates implementor
24
8
PARTNO
Indicates part number
4
12
REVISION
Indicates patch release
0
4
VARIANT
Indicates processor revision
20
4
HFSR
Hard Fault Status
0xD2C
32
read-write
n
0x0
0x0
DEBUGEVT
Debug event, and the Debug Fault Status Register has been updated.
31
1
DIS
DIS
0
EN
EN
1
FORCED
Configurable fault cannot be activated due to priority or it was disabled. Priority escalated to a HardFault.
30
1
DIS
DIS
0
EN
EN
1
VECTTBL
Fault was due to vector table read on exception processing
1
1
DIS
DIS
0
EN
EN
1
IABR0
IRQ0..31 Active Bit
0x300
32
read-write
n
0x0
0x0
ADC0
TBD
13
1
DIS
DIS
0
EN
EN
1
ADC1
TBD
14
1
DIS
DIS
0
EN
EN
1
DMADAC
TBD
31
1
DIS
DIS
0
EN
EN
1
DMAERROR
TBD
22
1
DIS
DIS
0
EN
EN
1
DMAI2CMRX
TBD
30
1
DIS
DIS
0
EN
EN
1
DMAI2CMTX
TBD
29
1
DIS
DIS
0
EN
EN
1
DMAI2CSRX
TBD
28
1
DIS
DIS
0
EN
EN
1
DMAI2CSTX
TBD
27
1
DIS
DIS
0
EN
EN
1
DMASPI1RX
TBD
24
1
DIS
DIS
0
EN
EN
1
DMASPI1TX
TBD
23
1
DIS
DIS
0
EN
EN
1
DMAUARTRX
TBD
26
1
DIS
DIS
0
EN
EN
1
DMAUARTTX
TBD
25
1
DIS
DIS
0
EN
EN
1
EXTINT0
TBD
1
1
DIS
DIS
0
EN
EN
1
EXTINT1
TBD
2
1
DIS
DIS
0
EN
EN
1
EXTINT2
TBD
3
1
DIS
DIS
0
EN
EN
1
EXTINT3
TBD
4
1
DIS
DIS
0
EN
EN
1
EXTINT4
TBD
5
1
DIS
DIS
0
EN
EN
1
EXTINT5
TBD
6
1
DIS
DIS
0
EN
EN
1
EXTINT6
TBD
7
1
DIS
DIS
0
EN
EN
1
EXTINT7
TBD
8
1
DIS
DIS
0
EN
EN
1
FEE
TBD
16
1
DIS
DIS
0
EN
EN
1
I2CM
TBD
21
1
DIS
DIS
0
EN
EN
1
I2CS
TBD
20
1
DIS
DIS
0
EN
EN
1
SINC2
TBD
15
1
DIS
DIS
0
EN
EN
1
SPI0
TBD
18
1
DIS
DIS
0
EN
EN
1
SPI1
TBD
19
1
DIS
DIS
0
EN
EN
1
T0
TBD
11
1
DIS
DIS
0
EN
EN
1
T1
TBD
12
1
DIS
DIS
0
EN
EN
1
T2
TBD
0
1
DIS
DIS
0
EN
EN
1
T3
TBD
9
1
DIS
DIS
0
EN
EN
1
UART
TBD
17
1
DIS
DIS
0
EN
EN
1
IABR1
IRQ32..63 Active Bit
0x304
32
read-write
n
0x0
0x0
DMAADC0
TBD
0
1
DIS
DIS
0
EN
EN
1
DMAADC1
TBD
1
1
DIS
DIS
0
EN
EN
1
DMASINC2
TBD
2
1
DIS
DIS
0
EN
EN
1
PWM0
TBD
4
1
DIS
DIS
0
EN
EN
1
PWM1
TBD
5
1
DIS
DIS
0
EN
EN
1
PWM2
TBD
6
1
DIS
DIS
0
EN
EN
1
PWMTRIP
TBD
3
1
DIS
DIS
0
EN
EN
1
ICER0
IRQ0..31 Clear_Enable
0x180
32
read-write
n
0x0
0x0
ADC0
TBD
13
1
DIS
DIS
0
EN
EN
1
ADC1
TBD
14
1
DIS
DIS
0
EN
EN
1
DMADAC
TBD
31
1
DIS
DIS
0
EN
EN
1
DMAERROR
TBD
22
1
DIS
DIS
0
EN
EN
1
DMAI2CMRX
TBD
30
1
DIS
DIS
0
EN
EN
1
DMAI2CMTX
TBD
29
1
DIS
DIS
0
EN
EN
1
DMAI2CSRX
TBD
28
1
DIS
DIS
0
EN
EN
1
DMAI2CSTX
TBD
27
1
DIS
DIS
0
EN
EN
1
DMASPI1RX
TBD
24
1
DIS
DIS
0
EN
EN
1
DMASPI1TX
TBD
23
1
DIS
DIS
0
EN
EN
1
DMAUARTRX
TBD
26
1
DIS
DIS
0
EN
EN
1
DMAUARTTX
TBD
25
1
DIS
DIS
0
EN
EN
1
EXTINT0
TBD
1
1
DIS
DIS
0
EN
EN
1
EXTINT1
TBD
2
1
DIS
DIS
0
EN
EN
1
EXTINT2
TBD
3
1
DIS
DIS
0
EN
EN
1
EXTINT3
TBD
4
1
DIS
DIS
0
EN
EN
1
EXTINT4
TBD
5
1
DIS
DIS
0
EN
EN
1
EXTINT5
TBD
6
1
DIS
DIS
0
EN
EN
1
EXTINT6
TBD
7
1
DIS
DIS
0
EN
EN
1
EXTINT7
TBD
8
1
DIS
DIS
0
EN
EN
1
FEE
TBD
16
1
DIS
DIS
0
EN
EN
1
I2CM
TBD
21
1
DIS
DIS
0
EN
EN
1
I2CS
TBD
20
1
DIS
DIS
0
EN
EN
1
SINC2
TBD
15
1
DIS
DIS
0
EN
EN
1
SPI0
TBD
18
1
DIS
DIS
0
EN
EN
1
SPI1
TBD
19
1
DIS
DIS
0
EN
EN
1
T0
TBD
11
1
DIS
DIS
0
EN
EN
1
T1
TBD
12
1
DIS
DIS
0
EN
EN
1
T2
TBD
0
1
DIS
DIS
0
EN
EN
1
T3
TBD
9
1
DIS
DIS
0
EN
EN
1
UART
TBD
17
1
DIS
DIS
0
EN
EN
1
ICER1
IRQ32..63 Clear_Enable
0x184
32
read-write
n
0x0
0x0
DMAADC0
TBD
0
1
DIS
DIS
0
EN
EN
1
DMAADC1
TBD
1
1
DIS
DIS
0
EN
EN
1
DMASINC2
TBD
2
1
DIS
DIS
0
EN
EN
1
PWM0
TBD
4
1
DIS
DIS
0
EN
EN
1
PWM1
TBD
5
1
DIS
DIS
0
EN
EN
1
PWM2
TBD
6
1
DIS
DIS
0
EN
EN
1
PWMTRIP
TBD
3
1
DIS
DIS
0
EN
EN
1
ICPR0
IRQ0..31 Clear_Pending
0x280
32
read-write
n
0x0
0x0
ADC0
TBD
13
1
DIS
DIS
0
EN
EN
1
ADC1
TBD
14
1
DIS
DIS
0
EN
EN
1
DMADAC
TBD
31
1
DIS
DIS
0
EN
EN
1
DMAERROR
TBD
22
1
DIS
DIS
0
EN
EN
1
DMAI2CMRX
TBD
30
1
DIS
DIS
0
EN
EN
1
DMAI2CMTX
TBD
29
1
DIS
DIS
0
EN
EN
1
DMAI2CSRX
TBD
28
1
DIS
DIS
0
EN
EN
1
DMAI2CSTX
TBD
27
1
DIS
DIS
0
EN
EN
1
DMASPI1RX
TBD
24
1
DIS
DIS
0
EN
EN
1
DMASPI1TX
TBD
23
1
DIS
DIS
0
EN
EN
1
DMAUARTRX
TBD
26
1
DIS
DIS
0
EN
EN
1
DMAUARTTX
TBD
25
1
DIS
DIS
0
EN
EN
1
EXTINT0
TBD
1
1
DIS
DIS
0
EN
EN
1
EXTINT1
TBD
2
1
DIS
DIS
0
EN
EN
1
EXTINT2
TBD
3
1
DIS
DIS
0
EN
EN
1
EXTINT3
TBD
4
1
DIS
DIS
0
EN
EN
1
EXTINT4
TBD
5
1
DIS
DIS
0
EN
EN
1
EXTINT5
TBD
6
1
DIS
DIS
0
EN
EN
1
EXTINT6
TBD
7
1
DIS
DIS
0
EN
EN
1
EXTINT7
TBD
8
1
DIS
DIS
0
EN
EN
1
FEE
TBD
16
1
DIS
DIS
0
EN
EN
1
I2CM
TBD
21
1
DIS
DIS
0
EN
EN
1
I2CS
TBD
20
1
DIS
DIS
0
EN
EN
1
SINC2
TBD
15
1
DIS
DIS
0
EN
EN
1
SPI0
TBD
18
1
DIS
DIS
0
EN
EN
1
SPI1
TBD
19
1
DIS
DIS
0
EN
EN
1
T0
TBD
11
1
DIS
DIS
0
EN
EN
1
T1
TBD
12
1
DIS
DIS
0
EN
EN
1
T2
TBD
0
1
DIS
DIS
0
EN
EN
1
T3
TBD
9
1
DIS
DIS
0
EN
EN
1
UART
TBD
17
1
DIS
DIS
0
EN
EN
1
ICPR1
IRQ32..63 Clear_Pending
0x284
32
read-write
n
0x0
0x0
DMAADC0
TBD
0
1
DIS
DIS
0
EN
EN
1
DMAADC1
TBD
1
1
DIS
DIS
0
EN
EN
1
DMASINC2
TBD
2
1
DIS
DIS
0
EN
EN
1
PWM0
TBD
4
1
DIS
DIS
0
EN
EN
1
PWM1
TBD
5
1
DIS
DIS
0
EN
EN
1
PWM2
TBD
6
1
DIS
DIS
0
EN
EN
1
PWMTRIP
TBD
3
1
DIS
DIS
0
EN
EN
1
ICSR
Interrupt Control and State Register
0xD04
32
read-write
n
0x0
0x0
ISRPENDING
Indicates if an external configurable is pending
22
1
DIS
DIS
0
EN
EN
1
ISRPREEMPT
If set, a pending exception will be serviced on exit from the debug halt state
23
1
DIS
DIS
0
EN
EN
1
NMIPENDSET
Setting this bit will activate an NMI
31
1
DIS
DIS
0
EN
EN
1
PENDSTCLR
Clear a pending SysTick
25
1
DIS
DIS
0
EN
EN
1
PENDSTSET
Set a pending SysTick. Reads back with current state
26
1
DIS
DIS
0
EN
EN
1
PENDSVCLR
Clear a pending PendSV interrupt
27
1
DIS
DIS
0
EN
EN
1
PENDSVSET
Set a pending PendSV interrupt
28
1
DIS
DIS
0
EN
EN
1
RETTOBASE
TBD
11
1
DIS
DIS
0
EN
EN
1
VECTACTIVE
Thread mode, or exception number
0
9
VECTPENDING
Indicates the exception number for the highest priority pending exception
12
9
ICTR
Shows the number of interrupt lines that the NVIC supports
0x4
32
read-only
n
0x0
0x0
INTLINESNUM
Total number of interrupt lines in groups of 32
0
4
IPR0
IRQ0..3 Priority
0x400
32
read-write
n
0x0
0x0
EXTINT0
Priority of interrupt number 1
8
8
EXTINT1
TBD
16
8
EXTINT2
TBD
24
8
T2
Priority of interrupt number 0
0
8
IPR1
IRQ4..7 Priority
0x404
32
read-write
n
0x0
0x0
EXTINT3
TBD
0
8
EXTINT4
TBD
8
8
EXTINT5
TBD
16
8
EXTINT6
TBD
24
8
IPR2
IRQ8..11 Priority
0x408
32
read-write
n
0x0
0x0
EXTINT7
TBD
0
8
T0
TBD
24
8
T3
TBD
8
8
IPR3
IRQ12..15 Priority
0x40C
32
read-write
n
0x0
0x0
ADC0
TBD
8
8
ADC1
TBD
16
8
SINC2
TBD
24
8
T1
TBD
0
8
IPR4
IRQ16..19 Priority
0x410
32
read-write
n
0x0
0x0
FEE
TBD
0
8
SPI0
TBD
16
8
SPI1
TBD
24
8
UART
TBD
8
8
IPR5
IRQ20..23 Priority
0x414
32
read-write
n
0x0
0x0
DMAERROR
TBD
16
8
DMASPI1TX
TBD
24
8
I2CM
TBD
8
8
I2CS
TBD
0
8
IPR6
IRQ24..27 Priority
0x418
32
read-write
n
0x0
0x0
DMAI2CSTX
TBD
24
8
DMASPI1RX
TBD
0
8
DMAUARTRX
TBD
16
8
DMAUARTTX
TBD
8
8
IPR7
IRQ28..31 Priority
0x41C
32
read-write
n
0x0
0x0
DMADAC
TBD
24
8
DMAI2CMRX
TBD
16
8
DMAI2CMTX
TBD
8
8
DMAI2CSRX
TBD
0
8
IPR8
IRQ32..35 Priority
0x420
32
read-write
n
0x0
0x0
DMAADC0
TBD
0
8
DMAADC1
TBD
8
8
DMASINC2
TBD
16
8
PWMTRIP
TBD
24
8
IPR9
IRQ36..39 Priority
0x424
32
read-write
n
0x0
0x0
PWM0
TBD
0
8
PWM1
TBD
8
8
PWM2
TBD
16
8
ISER0
IRQ0..31 Set_Enable
0x100
32
read-write
n
0x0
0x0
ADC0
TBD
13
1
DIS
DIS
0
EN
EN
1
ADC1
TBD
14
1
DIS
DIS
0
EN
EN
1
DMADAC
TBD
31
1
DIS
DIS
0
EN
EN
1
DMAERROR
TBD
22
1
DIS
DIS
0
EN
EN
1
DMAI2CMRX
TBD
30
1
DIS
DIS
0
EN
EN
1
DMAI2CMTX
TBD
29
1
DIS
DIS
0
EN
EN
1
DMAI2CSRX
TBD
28
1
DIS
DIS
0
EN
EN
1
DMAI2CSTX
TBD
27
1
DIS
DIS
0
EN
EN
1
DMASPI1RX
TBD
24
1
DIS
DIS
0
EN
EN
1
DMASPI1TX
TBD
23
1
DIS
DIS
0
EN
EN
1
DMAUARTRX
TBD
26
1
DIS
DIS
0
EN
EN
1
DMAUARTTX
TBD
25
1
DIS
DIS
0
EN
EN
1
EXTINT0
TBD
1
1
DIS
DIS
0
EN
EN
1
EXTINT1
TBD
2
1
DIS
DIS
0
EN
EN
1
EXTINT2
TBD
3
1
DIS
DIS
0
EN
EN
1
EXTINT3
TBD
4
1
DIS
DIS
0
EN
EN
1
EXTINT4
TBD
5
1
DIS
DIS
0
EN
EN
1
EXTINT5
TBD
6
1
DIS
DIS
0
EN
EN
1
EXTINT6
TBD
7
1
DIS
DIS
0
EN
EN
1
EXTINT7
TBD
8
1
DIS
DIS
0
EN
EN
1
FEE
TBD
16
1
DIS
DIS
0
EN
EN
1
I2CM
TBD
21
1
DIS
DIS
0
EN
EN
1
I2CS
TBD
20
1
DIS
DIS
0
EN
EN
1
SINC2
TBD
15
1
DIS
DIS
0
EN
EN
1
SPI0
TBD
18
1
DIS
DIS
0
EN
EN
1
SPI1
TBD
19
1
DIS
DIS
0
EN
EN
1
T0
TBD
11
1
DIS
DIS
0
EN
EN
1
T1
TBD
12
1
DIS
DIS
0
EN
EN
1
T2
TBD
0
1
DIS
DIS
0
EN
EN
1
T3
TBD
9
1
DIS
DIS
0
EN
EN
1
UART
TBD
17
1
DIS
DIS
0
EN
EN
1
ISER1
IRQ32..63 Set_Enable
0x104
32
read-write
n
0x0
0x0
DMAADC0
TBD
0
1
DIS
DIS
0
EN
EN
1
DMAADC1
TBD
1
1
DIS
DIS
0
EN
EN
1
DMASINC2
TBD
2
1
DIS
DIS
0
EN
EN
1
PWM0
TBD
4
1
DIS
DIS
0
EN
EN
1
PWM1
TBD
5
1
DIS
DIS
0
EN
EN
1
PWM2
TBD
6
1
DIS
DIS
0
EN
EN
1
PWMTRIP
TBD
3
1
DIS
DIS
0
EN
EN
1
ISPR0
IRQ0..31 Set_Pending
0x200
32
read-write
n
0x0
0x0
ADC0
TBD
13
1
DIS
DIS
0
EN
EN
1
ADC1
TBD
14
1
DIS
DIS
0
EN
EN
1
DMADAC
TBD
31
1
DIS
DIS
0
EN
EN
1
DMAERROR
TBD
22
1
DIS
DIS
0
EN
EN
1
DMAI2CMRX
TBD
30
1
DIS
DIS
0
EN
EN
1
DMAI2CMTX
TBD
29
1
DIS
DIS
0
EN
EN
1
DMAI2CSRX
TBD
28
1
DIS
DIS
0
EN
EN
1
DMAI2CSTX
TBD
27
1
DIS
DIS
0
EN
EN
1
DMASPI1RX
TBD
24
1
DIS
DIS
0
EN
EN
1
DMASPI1TX
TBD
23
1
DIS
DIS
0
EN
EN
1
DMAUARTRX
TBD
26
1
DIS
DIS
0
EN
EN
1
DMAUARTTX
TBD
25
1
DIS
DIS
0
EN
EN
1
EXTINT0
TBD
1
1
DIS
DIS
0
EN
EN
1
EXTINT1
TBD
2
1
DIS
DIS
0
EN
EN
1
EXTINT2
TBD
3
1
DIS
DIS
0
EN
EN
1
EXTINT3
TBD
4
1
DIS
DIS
0
EN
EN
1
EXTINT4
TBD
5
1
DIS
DIS
0
EN
EN
1
EXTINT5
TBD
6
1
DIS
DIS
0
EN
EN
1
EXTINT6
TBD
7
1
DIS
DIS
0
EN
EN
1
EXTINT7
TBD
8
1
DIS
DIS
0
EN
EN
1
FEE
TBD
16
1
DIS
DIS
0
EN
EN
1
I2CM
TBD
21
1
DIS
DIS
0
EN
EN
1
I2CS
TBD
20
1
DIS
DIS
0
EN
EN
1
SINC2
TBD
15
1
DIS
DIS
0
EN
EN
1
SPI0
TBD
18
1
DIS
DIS
0
EN
EN
1
SPI1
TBD
19
1
DIS
DIS
0
EN
EN
1
T0
TBD
11
1
DIS
DIS
0
EN
EN
1
T1
TBD
12
1
DIS
DIS
0
EN
EN
1
T2
TBD
0
1
DIS
DIS
0
EN
EN
1
T3
TBD
9
1
DIS
DIS
0
EN
EN
1
UART
TBD
17
1
DIS
DIS
0
EN
EN
1
ISPR1
IRQ32..63 Set_Pending
0x204
32
read-write
n
0x0
0x0
DMAADC0
TBD
0
1
DIS
DIS
0
EN
EN
1
DMAADC1
TBD
1
1
DIS
DIS
0
EN
EN
1
DMASINC2
TBD
2
1
DIS
DIS
0
EN
EN
1
PWM0
TBD
4
1
DIS
DIS
0
EN
EN
1
PWM1
TBD
5
1
DIS
DIS
0
EN
EN
1
PWM2
TBD
6
1
DIS
DIS
0
EN
EN
1
PWMTRIP
TBD
3
1
DIS
DIS
0
EN
EN
1
MMFAR
Mem Manage Address
0xD34
32
read-write
n
0x0
0x0
ADDRESS
Data address MPU faulted.
0
32
SCR
System Control Register
0xD10
32
read-write
n
0x0
0x0
SEVONPEND
TBD
4
1
DIS
DIS
0
EN
EN
1
SLEEPDEEP
Sleep deep bit
2
1
DIS
DIS
0
EN
EN
1
SLEEPONEXIT
Sleep on exit when returning from handler mode to thread mode
1
1
DIS
DIS
0
EN
EN
1
SHCSR
System Handler Control and State
0xD24
32
read-write
n
0x0
0x0
BUSFAULTACT
Reads as 1 if BusFault is Active.
1
1
DIS
DIS
0
EN
EN
1
BUSFAULTENA
Enable for BusFault.
17
1
DIS
DIS
0
EN
EN
1
BUSFAULTPENDED
Reads as 1 if BusFault is Pending
14
1
DIS
DIS
0
EN
EN
1
MEMFAULTACT
Reads as 1 if MemManage is Active
0
1
DIS
DIS
0
EN
EN
1
MEMFAULTENA
Enable for MemManage fault.
16
1
DIS
DIS
0
EN
EN
1
MEMFAULTPENDED
Reads as 1 if MemManage is Pending
13
1
DIS
DIS
0
EN
EN
1
MONITORACT
Reads as 1 if the Monitor is Active
8
1
DIS
DIS
0
EN
EN
1
PENDSVACT
Reads as 1 if PendSV is Active
10
1
DIS
DIS
0
EN
EN
1
SVCALLACT
Reads as 1 if SVCall is Active
7
1
DIS
DIS
0
EN
EN
1
SVCALLPENDED
Reads as 1 if SVCall is Pending
15
1
DIS
DIS
0
EN
EN
1
SYSTICKACT
Reads as 1 if SysTick is Active
11
1
DIS
DIS
0
EN
EN
1
USGFAULTACT
Reads as 1 if UsageFault is Active.
3
1
DIS
DIS
0
EN
EN
1
USGFAULTENA
Enable for UsageFault
18
1
DIS
DIS
0
EN
EN
1
USGFAULTPENDED
Reads as 1 if UsageFault is Pending
12
1
DIS
DIS
0
EN
EN
1
SHPR1
System Handler Priority Register 1
0xD18
32
read-write
n
0x0
0x0
PRI4
Priority of system handler 4 - MemManage
0
8
PRI5
Priority of system handler 5 - BusFault
8
8
PRI6
Priority of system handler 6 - UsageFault
16
8
PRI7
Priority of system handler 7 - reserved
24
8
SHPR2
System Handler Priority Register 2
0xD1C
32
read-write
n
0x0
0x0
PRI10
Priority of system handler 10 - reserved
16
8
PRI11
Priority of system handler 11 - SVCall
24
8
PRI8
Priority of system handler 8 - reserved
0
8
PRI9
Priority of system handler 9 - reserved
8
8
SHPR3
System Handler Priority Register 3
0xD20
32
read-write
n
0x0
0x0
PRI12
Priority of system handler 12 - DebugMonitor
0
8
PRI13
Priority of system handler 13 - reserved
8
8
PRI14
Priority of system handler 14 - PendSV
16
8
PRI15
Priority of system handler 15 - SysTick
24
8
STCR
SysTick Calibration Value Register
0x1C
32
read-only
n
0x0
0x0
NOREF
If reads as 1, the Reference clock is not provided
31
1
DIS
DIS
0
EN
EN
1
SKEW
If reads as 1, the calibration value for 10ms is inexact
30
1
DIS
DIS
0
EN
EN
1
TENMS
An optional Reload value to be used for 10ms (100Hz) timing
0
24
STCSR
SysTick Control and Status Register
0x10
32
read-write
n
0x0
0x0
CLKSOURCE
clock source used for SysTick
2
1
DIS
DIS
0
EN
EN
1
COUNTFLAG
Returns 1 if timer counted to 0 since last time this register was read
16
1
DIS
DIS
0
EN
EN
1
ENABLE
Enable bit
0
1
DIS
DIS
0
EN
EN
1
TICKINT
If 1, counting down to 0 will cause the SysTick exception to pended.
1
1
DIS
DIS
0
EN
EN
1
STCVR
SysTick Current Value Register
0x18
32
read-write
n
0x0
0x0
CURRENT
Current counter value
0
32
STIR
Software Trigger Interrupt Register
0xF00
32
write-only
n
0x0
0x0
INTID
The value written in this field is the interrupt to be triggered.
0
10
STRVR
SysTick Reload Value Register
0x14
32
read-write
n
0x0
0x0
RELOAD
Value to load into the Current Value register when the counter reaches 0
0
24
VTOR
Vector Table Offset Register
0xD08
32
read-write
n
0x0
0x0
TBLBASE
TBD
29
1
DIS
DIS
0
EN
EN
1
TBLOFF
TBD
7
22